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doc/asm.html
</p> <p> If a vector instruction takes a length or an index as an argument then it will be the first argument. For example, <code>VLEIF</code> <code>$1,</code> <code>$16,</code> <code>V2</code> will load the value sixteen into index one of <code>V2</code>. Care should be taken when using vector instructions to ensure that they are available at runtime.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 28 19:15:27 UTC 2023 - 36.3K bytes - Viewed (1) -
src/runtime/rand.go
"unsafe" _ "unsafe" // for go:linkname ) // OS-specific startup can set startupRand if the OS passes // random data to the process at startup time. // For example Linux passes 16 bytes in the auxv vector. var startupRand []byte // globalRand holds the global random state. // It is only used at startup and for creating new m's. // Otherwise the per-m random state should be used // by calling goodrand.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 31 14:32:47 UTC 2024 - 8K bytes - Viewed (0) -
src/crypto/aes/aes_test.go
for j := 0; j < 4; j++ { if x := td[j][i]; x != w { t.Fatalf("td[%d][%d] = %#x, want %#x", j, i, x, w) } w = w<<24 | w>>8 } } } // Test vectors are from FIPS 197: // https://csrc.nist.gov/publications/fips/fips197/fips-197.pdf // Appendix A of FIPS 197: Key expansion examples type KeyTest struct { key []byte enc []uint32
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 14:58:19 UTC 2024 - 12.5K bytes - Viewed (0) -
src/cmd/internal/obj/s390x/a.out.go
REG_F7 REG_F8 REG_F9 REG_F10 REG_F11 REG_F12 REG_F13 REG_F14 REG_F15 // Vector registers (VRs) - only available when the vector // facility is installed. // V0-V15 are aliases for F0-F15. // We keep them in a separate space to make printing etc. easier // If the code generator ever emits vector instructions it will // need to take into account the aliasing. REG_V0 REG_V1 REG_V2 REG_V3
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Sep 05 16:41:03 UTC 2023 - 12.4K bytes - Viewed (0) -
src/math/big/arith_386.s
// license that can be found in the LICENSE file. //go:build !math_big_pure_go #include "textflag.h" // This file provides fast assembly versions for the elementary // arithmetic operations on vectors implemented in arith.go. // func addVV(z, x, y []Word) (c Word) TEXT ·addVV(SB),NOSPLIT,$0 MOVL z+0(FP), DI MOVL x+12(FP), SI MOVL y+24(FP), CX MOVL z_len+4(FP), BP MOVL $0, BX // i = 0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 4K bytes - Viewed (0) -
src/image/geom.go
} // Add returns the vector p+q. func (p Point) Add(q Point) Point { return Point{p.X + q.X, p.Y + q.Y} } // Sub returns the vector p-q. func (p Point) Sub(q Point) Point { return Point{p.X - q.X, p.Y - q.Y} } // Mul returns the vector p*k. func (p Point) Mul(k int) Point { return Point{p.X * k, p.Y * k} } // Div returns the vector p/k. func (p Point) Div(k int) Point {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 12:02:45 UTC 2023 - 7.3K bytes - Viewed (0) -
src/math/big/arith_arm.s
// license that can be found in the LICENSE file. //go:build !math_big_pure_go #include "textflag.h" // This file provides fast assembly versions for the elementary // arithmetic operations on vectors implemented in arith.go. // func addVV(z, x, y []Word) (c Word) TEXT ·addVV(SB),NOSPLIT,$0 ADD.S $0, R0 // clear carry flag MOVW z+0(FP), R1 MOVW z_len+4(FP), R4 MOVW x+12(FP), R2 MOVW y+24(FP), R3
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 4K bytes - Viewed (0) -
src/runtime/os_netbsd.go
auxvp := (*[1 << 28]uintptr)(add(unsafe.Pointer(argv), uintptr(n)*goarch.PtrSize)) pairs := sysauxv(auxvp[:]) auxv = auxvp[: pairs*2 : pairs*2] } const ( _AT_NULL = 0 // Terminates the vector _AT_PAGESZ = 6 // Page size in bytes ) func sysauxv(auxv []uintptr) (pairs int) { var i int for i = 0; auxv[i] != _AT_NULL; i += 2 { tag, val := auxv[i], auxv[i+1] switch tag {
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 19:53:03 UTC 2024 - 10.1K bytes - Viewed (0) -
src/crypto/sha256/sha256block_amd64.s
#define m1 X4 #define m2 X5 #define m3 X6 #define m4 X7 #define shufMask X8 // input data endian conversion control mask #define abefSave X9 // digest hash vector inter-block buffer abef #define cdghSave X10 // digest hash vector inter-block buffer cdgh #define nop(m,a) // nop instead of final SHA256MSG1 for first and last few rounds #define sha256msg1(m,a) \ // final SHA256MSG1 for middle rounds that require it
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 47.3K bytes - Viewed (0) -
src/internal/bytealg/count_ppc64x.s
BLT tail // Jump to the small string case SRD $5, R4, R20 MOVD R20, CTR MOVD $16, R21 XXLXOR V4, V4, V4 XXLXOR V5, V5, V5 PCALIGN $16 cmploop: LXVD2X (R0)(R3), V0 // Count 32B per loop with two vector accumulators. LXVD2X (R21)(R3), V2 VCMPEQUB V2, V1, V2 VCMPEQUB V0, V1, V0 VPOPCNTD V2, V2 // A match is 0xFF or 0. Count the bits into doubleword buckets. VPOPCNTD V0, V0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Aug 14 20:30:44 UTC 2023 - 3.6K bytes - Viewed (0)