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  1. .github/ISSUE_TEMPLATE/feature_addition_request.yaml

            #### Ubiquity: provide concrete use cases
    
    
            Did you *actually* encounter the need for this feature in a real-world scenario, or is it
            just a feature that seems like a sensible addition to Guava?
    
    
            Before new features get added to Guava, we really want to be sure that it's for a use case
            that actually comes up in the real world. We want to hear the real-world use case so the
    Registered: Wed Jun 12 16:38:11 UTC 2024
    - Last Modified: Fri Nov 17 18:47:47 UTC 2023
    - 5.8K bytes
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  2. src/cmd/asm/internal/asm/testdata/amd64error.s

    	// TODO(quasilyte): improve error message (#21860).
    	// "invalid VSIB address (missing vector index)"
    	VPGATHERQQ Y2, (BP), Y1         // ERROR "invalid instruction"
    	// AVX2GATHER mask/index/dest #UD cases.
    	VPGATHERQQ Y2, (BP)(X2*2), Y2   // ERROR "mask, index, and destination registers should be distinct"
    	VPGATHERQQ Y2, (BP)(X2*2), Y7   // ERROR "mask, index, and destination registers should be distinct"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Jun 14 00:03:57 UTC 2023
    - 8.9K bytes
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  3. .github/workflows/ci.yml

            shell: bash
            run: ./mvnw -B -P!standard-with-extra-repos verify -U -Dmaven.javadoc.skip=true -f $ROOT_POM
          - name: 'Print Surefire reports'
            # Note: Normally a step won't run if the job has failed, but this causes it to
            if: ${{ failure() }}
            shell: bash
            run: ./util/print_surefire_reports.sh
          - name: 'Integration Test'
            if: matrix.java == 11
            shell: bash
    Registered: Wed Jun 12 16:38:11 UTC 2024
    - Last Modified: Fri May 17 16:25:39 UTC 2024
    - 3.5K bytes
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  4. src/cmd/asm/internal/asm/testdata/mips64.s

    //
    // RET
    //
    //	LRETRN	comma // asm doesn't support the trailing comma.
    //	{
    //		outcode(int($1), &nullgen, 0, &nullgen);
    //	}
    	SYSCALL
    	BEQ	R1, 2(PC)
    	RET
    
    
    // More JMP/JAL cases, and canonical names JMP, CALL.
    
    	JAL	foo(SB) // CALL foo(SB)
    	BEQ	R1, 2(PC)
    	JMP	foo(SB)
    	CALL	foo(SB)
    	RET	foo(SB)
    
    	// unary operation
    	NEGW	R1, R2 // 00011023
    	NEGV	R1, R2 // 0001102f
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 12.4K bytes
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  5. src/cmd/asm/internal/asm/testdata/arm.s

    //	}
    	PLD	(R1)
    	PLD	4(R1)
    
    //
    // RET
    //
    //	LTYPEA cond
    //	{
    //		outcode($1, $2, &nullgen, 0, &nullgen);
    //	}
    	BEQ	2(PC)
    	RET
    
    // More B/BL cases, and canonical names JMP, CALL.
    
    	BEQ	2(PC)
    	B	foo(SB) // JMP foo(SB)
    	BL	foo(SB) // CALL foo(SB)
    	BEQ	2(PC)
    	JMP	foo(SB)
    	CALL	foo(SB)
    
    // CMPF and CMPD are special.
    	CMPF F1, F2
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 15 20:51:01 UTC 2023
    - 69K bytes
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  6. .github/ISSUE_TEMPLATE/feature_enhancement_request.yaml

            that it's for a use case that actually comes up in the real world. We want to hear the
            real-world use case so the community can discuss and debate whether this feature is actually
            the *best* way to address the real use case, or whether or not a different approach might be
            more appropriate.
    
    
            It's okay if you can't provide complete context on a use case. We understand if you are not
    Registered: Wed Jun 12 16:38:11 UTC 2024
    - Last Modified: Fri Nov 17 18:47:47 UTC 2023
    - 3.9K bytes
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  7. src/cmd/asm/internal/asm/testdata/ppc64.s

    // available in cmd/internal/obj/ppc64/asm9.go with
    // their valid instruction encodings.
    
    #include "../../../../../runtime/textflag.h"
    
    // In case of index mode instructions, usage of
    // (Rx)(R0) is equivalent to (Rx+R0)
    // In case of base+displacement mode instructions if
    // the offset is 0, usage of (Rx) is equivalent to 0(Rx)
    TEXT asmtest(SB),DUPOK|NOSPLIT,$0
    	// move constants
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 17 21:53:50 UTC 2024
    - 50.2K bytes
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  8. src/cmd/cgo/internal/test/stubtest_linux_ppc64le.S

    // NOTOC -> dynamic [P8/pie]:     A P8 compatible, PIC stub is generated
    //
    //
    // Some notes about other cases:
    //   TOC -> TOC, NOTOC -> NOTOC, NOTOC -> TOC  local calls do not require require call stubs.
    //   TOC -> NOTOC (R2 is preserved, st_other==0): A special case where a call stub is not needed.
    
    // This test requires a binutils with power10 and ELFv2 1.5 support. This is earliest verified version.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Sep 22 15:06:17 UTC 2023
    - 3.7K bytes
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  9. src/cmd/asm/internal/asm/testdata/mips.s

    	//
    	// RET
    	//
    	//	LRETRN	comma // asm doesn't support the trailing comma.
    	//	{
    	//		outcode(int($1), &nullgen, 0, &nullgen);
    	//	}
    	SYSCALL
    	BEQ	R1, 2(PC)
    	RET
    
    
    	// More JMP/JAL cases, and canonical names JMP, CALL.
    
    	JAL	foo(SB)	// CALL foo(SB)
    	BEQ	R1, 2(PC)
    	JMP	foo(SB)
    	CALL	foo(SB)
    	RET	foo(SB)
    
    	// unary operation
    	NEGW	R1, R2 // 00011023
    	CLZ	R1, R2 // 70221020
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 6.7K bytes
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  10. src/cmd/asm/internal/asm/testdata/amd64dynlinkerror.s

    one:
    	MOVL $0, R15
    	JMP two
    
    // Ensure 3-arg instructions get GOT-rewritten without errors.
    // See issue 58735.
    TEXT ·a13(SB), 0, $0-0
    	MULXQ runtime·writeBarrier(SB), AX, CX
    	RET
    
    // Various special cases in the use-R15-after-global-access-when-dynlinking check.
    // See issue 58632.
    TEXT ·a14(SB), 0, $0-0
    	CMPL runtime·writeBarrier(SB), $0
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 15 20:45:41 UTC 2023
    - 4.8K bytes
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