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Results 1 - 10 of 17 for reg2 (0.06 sec)
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src/cmd/compile/internal/ppc64/ssa.go
p.Reg = r1 p.To.Type = obj.TYPE_REG p.To.Reg = r case ssa.OpPPC64ADDZE: p := s.Prog(v.Op.Asm()) p.From.Type = obj.TYPE_REG p.From.Reg = v.Args[0].Reg() p.To.Type = obj.TYPE_REG p.To.Reg = v.Reg0() case ssa.OpPPC64ADDZEzero, ssa.OpPPC64SUBZEzero: p := s.Prog(v.Op.Asm()) p.From.Type = obj.TYPE_REG p.From.Reg = ppc64.REG_R0 p.To.Type = obj.TYPE_REG p.To.Reg = v.Reg()
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 55.4K bytes - Viewed (0) -
src/cmd/internal/obj/riscv/obj.go
return encodeR4(ins.as, regF(ins.rs1), regF(ins.rs2), regF(ins.rs3), regF(ins.rd), ins.funct3, ins.funct7) } func encodeRFFI(ins *instruction) uint32 { return encodeR(ins.as, regF(ins.rs1), regF(ins.rs2), regI(ins.rd), ins.funct3, ins.funct7) } func encodeRFI(ins *instruction) uint32 { return encodeR(ins.as, regF(ins.rs2), 0, regI(ins.rd), ins.funct3, ins.funct7) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Sun Apr 07 03:32:27 UTC 2024 - 77K bytes - Viewed (0) -
src/crypto/internal/nistec/p256_asm_ppc64le.s
VADDECUQ T1, RED2, CAR1, CAR2 // VACCCQ T1, RED2, CAR1, CAR2 VADDEUQM T1, RED2, CAR1, T1 // VACQ T1, RED2, CAR1, T1 VADDUQM T2, CAR2, T2 // VAQ T2, CAR2, T2 // Second round VPERM T1, T0, SEL1, RED2 // d1 d0 d1 d0 VPERM ZER, RED2, SEL2, RED1 // 0 d1 d0 0 VSUBUQM RED2, RED1, RED2 // VSQ RED1, RED2, RED2 // Guaranteed not to underflow
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 56.5K bytes - Viewed (0) -
src/crypto/internal/nistec/p256_asm_s390x.s
VPERM ZER, RED2, SEL2, RED1 // 0 d1 d0 0 VSQ RED1, RED2, RED2 // Guaranteed not to underflow VSLDB $8, T1, T0, T0 VSLDB $8, T2, T1, T1 VACCQ T0, RED1, CAR1 VAQ T0, RED1, T0 VACCCQ T1, RED2, CAR1, CAR2 VACQ T1, RED2, CAR1, T1 VAQ T2, CAR2, T2 // Third round VPERM T1, T0, SEL1, RED2 // d1 d0 d1 d0 VPERM ZER, RED2, SEL2, RED1 // 0 d1 d0 0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 55.4K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/regalloc.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 17:49:56 UTC 2023 - 87.2K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/decode.go
switch aop { default: return nil case arg_Da: return D0 + Reg((x>>10)&(1<<5-1)) case arg_Dd: return D0 + Reg(x&(1<<5-1)) case arg_Dm: return D0 + Reg((x>>16)&(1<<5-1)) case arg_Dn: return D0 + Reg((x>>5)&(1<<5-1)) case arg_Hd: return H0 + Reg(x&(1<<5-1)) case arg_Hn: return H0 + Reg((x>>5)&(1<<5-1)) case arg_IAddSub: imm12 := (x >> 10) & (1<<12 - 1)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon May 16 22:24:28 UTC 2022 - 76.9K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
{name: "FMOVDfpgp", argLength: 1, reg: fpgp, asm: "FMOVD"}, // move float64 to int64 (no conversion) {name: "FMOVSgpfp", argLength: 1, reg: gpfp, asm: "FMOVS"}, // move 32bits from int to float reg (no conversion) {name: "FMOVSfpgp", argLength: 1, reg: fpgp, asm: "FMOVS"}, // move 32bits from float to int reg, zero extend (no conversion) // conversions
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0) -
tensorflow/c/c_api_test.cc
*added_node = node_def; EXPECT_EQ(graph_def.DebugString(), graph_def2.DebugString()); // Look up some nodes by name. TF_Operation* neg2 = TF_GraphOperationByName(graph, "neg"); EXPECT_TRUE(neg == neg2); NodeDef node_def2; ASSERT_TRUE(GetNodeDef(neg2, &node_def2)); EXPECT_EQ(node_def.DebugString(), node_def2.DebugString()); TF_Operation* feed2 = TF_GraphOperationByName(graph, "feed");
Registered: Sun Jun 16 05:45:23 UTC 2024 - Last Modified: Mon Apr 15 03:35:10 UTC 2024 - 96.9K bytes - Viewed (0) -
src/regexp/testdata/testregex.c
#pragma prototyped noticed /* * regex(3) test harness * * build: cc -o testregex testregex.c * help: testregex --man * note: REG_* features are detected by #ifdef; if REG_* are enums * then supply #define REG_foo REG_foo for each enum REG_foo * * Glenn Fowler <******@****.***> * AT&T Research * * PLEASE: publish your tests so everyone can benefit * * The following license covers testregex.c and all associated test data.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Sep 08 04:08:51 UTC 2014 - 51.3K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/debug.go
state.f.Fatalf("at %v: slot %v in register %v with no location entry", v, state.slots[slot], &state.registers[reg]) continue } regs := last.Registers &^ (1 << reg) setSlot(slot, VarLoc{regs, last.StackOffset}) } locs.registers[reg] = locs.registers[reg][:0] } switch { case v.Op == OpVarDef: n := v.Aux.(*ir.Name) if ir.IsSynthetic(n) { break }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Jun 10 19:44:43 UTC 2024 - 58.4K bytes - Viewed (0)