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src/cmd/compile/internal/ssa/_gen/ARM64.rules
(BitRev16 x) => (SRLconst [48] (RBIT <typ.UInt64> x)) (BitRev8 x) => (SRLconst [56] (RBIT <typ.UInt64> x)) // In fact, UMOD will be translated into UREM instruction, and UREM is originally translated into // UDIV and MSUB instructions. But if there is already an identical UDIV instruction just before or // after UREM (case like quo, rem := z/y, z%y), then the second UDIV instruction becomes redundant.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0)