}
	}

	// Mark nonpreemptible instruction sequences.
	// The 2-instruction TLS access sequence
	//	MOVQ TLS, BX
	//	MOVQ 0(BX)(TLS*1), BX
	// is not async preemptible, as if it is preempted and resumed on
	// a different thread, the TLS address may become invalid.
	if !CanUse1InsnTLS(ctxt) {
		useTLS := func(p *obj.Prog) bool {
			// Only need to mark the second instruction, which has

	size  int8   // Text space in bytes to lay operation

	// A prefixed instruction is generated by this opcode. This cannot be placed
	// across a 64B PC address. Opcodes should not translate to more than one
	// prefixed instruction. The prefixed instruction should be written first
	// (e.g when Optab.size > 8).
	ispfx bool

	asmout func(*ctxt9, *obj.Prog, *Optab, *[5]uint32)
}

// isRestartable returns whether p is a multi-instruction sequence that,
// if preempted, can be restarted.
func (c *ctxt7) isRestartable(p *obj.Prog) bool {
	if c.isUnsafePoint(p) {
		return false
	}
	// If p is a multi-instruction sequence with uses REGTMP inserted by
	// the assembler in order to materialize a large constant/offset, we
	// can restart p (at the start of the instruction sequence), recompute

// In fact, UMOD will be translated into UREM instruction, and UREM is originally translated into
// UDIV and MSUB instructions. But if there is already an identical UDIV instruction just before or
// after UREM (case like quo, rem := z/y, z%y), then the second UDIV instruction becomes redundant.
// The purpose of this rule is to have this extra UDIV instruction removed in CSE pass.

	}

	switch {
	case ctxt.IsARM():
		return n * 20 // Trampolines in ARM range from 3 to 5 instructions.
	case ctxt.IsARM64():
		return n * 12 // Trampolines in ARM64 are 3 instructions.
	case ctxt.IsPPC64():
		return n * 16 // Trampolines in PPC64 are 4 instructions.
	case ctxt.IsRISCV64():
		return n * 8 // Trampolines in RISCV64 are 2 instructions.
	}
	panic("unreachable")
}

  if (return_ops.size() != 1) return failure();

  // Find the return type.
  auto return_op = return_ops.front();

  // Manually fold tf.Cast that precedes the return instruction and only differs
  // in shape refinement level.
  bool changed = false;
  for (OpOperand& arg_op : return_op.getOperation()->getOpOperands()) {
    Operation* arg_defining_op = arg_op.get().getDefiningOp();

//	GOMIPS64
//		For GOARCH=mips64{,le}, whether to use floating point instructions.
//		Valid values are hardfloat (default), softfloat.
//	GOPPC64
//		For GOARCH=ppc64{,le}, the target ISA (Instruction Set Architecture).
//		Valid values are power8 (default), power9, power10.
//	GORISCV64
//		For GOARCH=riscv64, the RISC-V user-mode application profile for which
//		to compile. Valid values are rva20u64 (default), rva22u64.

// Simplifications that apply to all backend architectures. As an example, this
// Go source code
//
// y := 0 * x
//
// can be translated into y := 0 without losing any information, which saves a
// pointless multiplication instruction. Other .rules files in this directory
// (for example AMD64.rules) contain rules specific to the architecture in the
// filename. The rules here apply to every architecture.
//

	}

	memclrNoHeapPointers(unsafe.Pointer(&newg.sched), unsafe.Sizeof(newg.sched))
	newg.sched.sp = sp
	newg.stktopsp = sp
	newg.sched.pc = abi.FuncPCABI0(goexit) + sys.PCQuantum // +PCQuantum so that previous instruction is in same function
	newg.sched.g = guintptr(unsafe.Pointer(newg))
	gostartcallfn(&newg.sched, fn)
	newg.parentGoid = callergp.goid
	newg.gopc = callerpc
	newg.ancestors = saveAncestors(callergp)

          "can "
          "enable TF kernels fallback using TF Select. See instructions: "
          "https://www.tensorflow.org/lite/guide/ops_select \n" +
          failed_flex_ops_summary + "\n";
    if (!failed_custom_ops_.empty())
      err +=
          "\nSome ops in the model are custom ops, "
          "See instructions to implement "
          "custom ops: https://www.tensorflow.org/lite/guide/ops_custom \n" +