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Results 1 - 10 of 53 for divd (0.13 sec)
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test/codegen/arithmetic.go
d += e } return d, e } func NoFix32A(divr int32) (int32, int32) { var d int32 = 42 var e int32 = 84 if divr > 5 { // amd64:-"JMP" // 386:-"JMP" d /= divr // amd64:-"JMP" // 386:-"JMP" e %= divr d += e } return d, e } func NoFix32B(divd int32) (int32, int32) { var d int32 var e int32 var divr int32 = -1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri May 17 15:28:00 UTC 2024 - 15.2K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go
return true case MULLW, MULLWCC, MULHW, MULHWCC, MULLD, MULLDCC, MULHD, MULHDCC, MULLWO, MULLWOCC, MULHWU, MULHWUCC, MULLDO, MULLDOCC: return true case DIVD, DIVDCC, DIVDU, DIVDUCC, DIVDE, DIVDECC, DIVDEU, DIVDEUCC, DIVDO, DIVDOCC, DIVDUO, DIVDUOCC: return true case MODUD, MODSD, MODUW, MODSW: return true
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 22 17:16:14 UTC 2022 - 10.9K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/s390x.s
MLGR R1, R2 // b9860021 DIVD R1, R2 // b90400b2b90d00a1b904002b DIVD R1, R2, R3 // b90400b2b90d00a1b904003b DIVW R4, R5 // b90400b5b91d00a4b904005b DIVW R4, R5, R6 // b90400b5b91d00a4b904006b DIVDU R7, R8 // a7a90000b90400b8b98700a7b904008b DIVDU R7, R8, R9 // a7a90000b90400b8b98700a7b904009b
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Nov 22 03:55:32 UTC 2023 - 21.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPSOps.go
{name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1 {name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"}, // arg0 / arg1 {name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"}, // arg0 / arg1 {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0 & arg1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 14:43:03 UTC 2023 - 24K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/LOONG64Ops.go
{name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1 {name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"}, // arg0 / arg1 {name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"}, // arg0 / arg1 {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0 & arg1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 21 19:04:19 UTC 2023 - 25.2K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/MIPS64Ops.go
{name: "MULD", argLength: 2, reg: fp21, asm: "MULD", commutative: true}, // arg0 * arg1 {name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"}, // arg0 / arg1 {name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"}, // arg0 / arg1 {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true}, // arg0 & arg1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 24 03:36:31 UTC 2023 - 25.5K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/arm/armasm/plan9x.go
{VNMLA_EQ_F64, []int{2, 1, 0}, "VNMLA", "NMULAD"}, {VNMLS_EQ_F32, []int{2, 1, 0}, "VNMLS", "NMULSF"}, {VNMLS_EQ_F64, []int{2, 1, 0}, "VNMLS", "NMULSD"}, {VDIV_EQ_F32, []int{2, 1, 0}, "VDIV", "DIVF"}, {VDIV_EQ_F64, []int{2, 1, 0}, "VDIV", "DIVD"}, {VNEG_EQ_F32, []int{1, 0}, "VNEG", "NEGF"}, {VNEG_EQ_F64, []int{1, 0}, "VNEG", "NEGD"}, {VABS_EQ_F32, []int{1, 0}, "VABS", "ABSF"}, {VABS_EQ_F64, []int{1, 0}, "VABS", "ABSD"},
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 11.9K bytes - Viewed (0) -
src/runtime/sys_linux_s390x.s
MOVD $r+8(FP), R2 MOVW flags+0(FP), R3 MOVW $SYS_pipe2, R1 SYSCALL MOVW R2, errno+16(FP) RET TEXT runtimeĀ·usleep(SB),NOSPLIT,$16-4 MOVW usec+0(FP), R2 MOVD R2, R4 MOVW $1000000, R3 DIVD R3, R2 MOVD R2, 8(R15) MOVW $1000, R3 MULLD R2, R3 SUB R3, R4 MOVD R4, 16(R15) // nanosleep(&ts, 0) ADD $8, R15, R2 MOVW $0, R3 MOVW $SYS_nanosleep, R1 SYSCALL RET
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 24 18:53:44 UTC 2023 - 12.5K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARMOps.go
{name: "NMULD", argLength: 2, reg: fp21, asm: "NMULD", commutative: true}, // -(arg0 * arg1) {name: "DIVF", argLength: 2, reg: fp21, asm: "DIVF"}, // arg0 / arg1 {name: "DIVD", argLength: 2, reg: fp21, asm: "DIVD"}, // arg0 / arg1 {name: "MULAF", argLength: 3, reg: fp31, asm: "MULAF", resultInArg0: true}, // arg0 + (arg1 * arg2)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 41K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/PPC64Ops.go
{name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS"}, // arg0/arg1 {name: "DIVD", argLength: 2, reg: gp21, asm: "DIVD", typ: "Int64"}, // arg0/arg1 (signed 64-bit) {name: "DIVW", argLength: 2, reg: gp21, asm: "DIVW", typ: "Int32"}, // arg0/arg1 (signed 32-bit) {name: "DIVDU", argLength: 2, reg: gp21, asm: "DIVDU", typ: "Int64"}, // arg0/arg1 (unsigned 64-bit)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 19:59:38 UTC 2024 - 43.8K bytes - Viewed (0)