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Results 1 - 8 of 8 for mmx0 (0.04 sec)
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src/cmd/internal/obj/ppc64/a.out.go
REG_CR0 REG_CR1 REG_CR2 REG_CR3 REG_CR4 REG_CR5 REG_CR6 REG_CR7 // MMA accumulator registers, these shadow VSR 0-31 // e.g MMAx shadows VSRx*4-VSRx*4+3 or // MMA0 shadows VSR0-VSR3 REG_A0 REG_A1 REG_A2 REG_A3 REG_A4 REG_A5 REG_A6 REG_A7 REG_MSR REG_FPSCR REG_CR REG_SPECIAL = REG_CR0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 01 18:50:29 UTC 2024 - 16K bytes - Viewed (0) -
src/runtime/asm_386.s
notintel: // Load EAX=1 cpuid flags MOVL $1, AX CPUID MOVL CX, DI // Move to global variable clobbers CX when generating PIC MOVL AX, runtime·processorVersionInfo(SB) // Check for MMX support TESTL $(1<<23), DX // MMX JZ bad_proc nocpuinfo: // if there is an _cgo_init, call it to let it // initialize and to set up GS. if not, // we set up GS ourselves. MOVL _cgo_init(SB), AX TESTL AX, AX
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 15 15:45:13 UTC 2024 - 43.1K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/x86/x86asm/inst.go
R14 R15 // Instruction pointer. IP // 16-bit EIP // 32-bit RIP // 64-bit // 387 floating point registers. F0 F1 F2 F3 F4 F5 F6 F7 // MMX registers. M0 M1 M2 M3 M4 M5 M6 M7 // XMM registers. X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 10.6K bytes - Viewed (0) -
src/sync/atomic/doc.go
// // [the Go memory model]: https://go.dev/ref/mem package atomic import ( "unsafe" ) // BUG(rsc): On 386, the 64-bit functions use instructions unavailable before the Pentium MMX. // // On non-Linux ARM, the 64-bit functions use instructions unavailable before the ARMv6k core. // // On ARM, 386, and 32-bit MIPS, it is the caller's responsibility to arrange
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jun 07 21:14:51 UTC 2024 - 11.7K bytes - Viewed (0) -
src/runtime/mgcscavenge_test.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 25 19:53:03 UTC 2024 - 25.2K bytes - Viewed (0) -
src/cmd/vendor/golang.org/x/arch/x86/x86asm/gnu.go
IP: "%ip", EIP: "%eip", RIP: "%rip", F0: "%st", F1: "%st(1)", F2: "%st(2)", F3: "%st(3)", F4: "%st(4)", F5: "%st(5)", F6: "%st(6)", F7: "%st(7)", M0: "%mm0", M1: "%mm1", M2: "%mm2", M3: "%mm3", M4: "%mm4", M5: "%mm5", M6: "%mm6", M7: "%mm7", X0: "%xmm0", X1: "%xmm1", X2: "%xmm2", X3: "%xmm3", X4: "%xmm4",
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:33 UTC 2023 - 21.4K bytes - Viewed (0) -
doc/asm.html
TEXT runtime·atomicload64(SB), NOSPLIT, $0-12 MOVL ptr+0(FP), AX TESTL $7, AX JZ 2(PC) MOVL 0, AX // crash with nil ptr deref LEAL ret_lo+4(FP), BX // MOVQ (%EAX), %MM0 BYTE $0x0f; BYTE $0x6f; BYTE $0x00 // MOVQ %MM0, 0(%EBX) BYTE $0x0f; BYTE $0x7f; BYTE $0x03 // EMMS BYTE $0x0F; BYTE $0x77 RET
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Nov 28 19:15:27 UTC 2023 - 36.3K bytes - Viewed (1) -
src/cmd/vendor/golang.org/x/arch/x86/x86asm/decode.go
inst.PCRelOff = dispoff } } else { base := baseReg[x] index := Reg(rm) switch decodeOp(x) { case xArgMmM32, xArgMmM64, xArgMm2M64: // There are only 8 MMX registers, so these ignore the REX.X bit. index &= 7 case xArgRM8: if rex != 0 && index >= 4 { rexUsed |= PrefixREX index -= 4 base = SPB } case xArgYmm2M256:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 10 18:59:52 UTC 2023 - 45.1K bytes - Viewed (0)