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Results 21 - 30 of 30 for Zr (0.03 sec)
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src/cmd/internal/obj/arm64/list7.go
} func rconv(r int) string { ext := (r >> 5) & 7 if r == REGG { return "g" } switch { case REG_R0 <= r && r <= REG_R30: return fmt.Sprintf("R%d", r-REG_R0) case r == REG_R31: return "ZR" case REG_F0 <= r && r <= REG_F31: return fmt.Sprintf("F%d", r-REG_F0) case REG_V0 <= r && r <= REG_V31: return fmt.Sprintf("V%d", r-REG_V0) case r == REGSP: return "RSP"
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 18 17:56:30 UTC 2023 - 6K bytes - Viewed (0) -
src/runtime/memmove_arm64.s
STP (R12, R13), -16(R5) RET // Copy more than 128 bytes. copy_long: ADD R1, R2, R4 // R4 points just past the last source byte ADD R0, R2, R5 // R5 points just past the last destination byte MOVD ZR, R7 MOVD ZR, R8 CMP $1024, R2 BLT backward_check // feature detect to decide how to align MOVBU runtimeĀ·arm64UseAlignedLoads(SB), R6 CBNZ R6, use_aligned_loads MOVD R0, R7 MOVD R5, R8
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Mar 18 18:26:13 UTC 2022 - 6K bytes - Viewed (0) -
src/runtime/unsafepoint_test.go
case "arm64": if parts[3] == "MOVWU" { // The unpreemptible region starts after the // load of runtime.writeBarrier. startedWB = true } if parts[3] == "MOVD" && parts[4] == "ZR," { // The unpreemptible region ends after the // write of nil. doneWB = true } case "amd64": if parts[3] == "CMPL" { startedWB = true }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Aug 11 20:24:56 UTC 2023 - 3.3K bytes - Viewed (0) -
src/internal/bytealg/equal_arm64.s
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jan 24 16:07:25 UTC 2024 - 2.5K bytes - Viewed (0) -
docs/debugging/inspect/export.go
f, e := os.Open(downloadPath) if e != nil { return e } if st, e := f.Stat(); e == nil { sz = st.Size() } defer f.Close() r = f zr, e := zip.NewReader(r.(io.ReaderAt), sz) if e != nil { return e } for _, file := range zr.File { if !file.FileInfo().IsDir() && strings.HasSuffix(file.Name, "xl.meta") { r, e := file.Open() if e != nil { return e }
Registered: Sun Jun 16 00:44:34 UTC 2024 - Last Modified: Tue Nov 08 15:58:02 UTC 2022 - 9.1K bytes - Viewed (0) -
src/cmd/internal/obj/arm64/doc.go
LDAXRB (R19), R16 <=> ldaxrb w16, [x19] NOOP <=> nop # Register mapping rules 1. All basic register names are written as Rn. 2. Go uses ZR as the zero register and RSP as the stack pointer. 3. Bn, Hn, Dn, Sn and Qn instructions are written as Fn in floating-point instructions and as Vn in SIMD instructions. # Argument mapping rules
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Aug 07 00:21:42 UTC 2023 - 9.6K bytes - Viewed (0) -
src/crypto/tls/testdata/Server-TLSv13-X25519
000000f0 0f d0 ec dd d4 75 57 0d 3f 7e a3 a4 40 f7 67 d2 |.....uW.?~..@.g.| 00000100 22 ba 5f a1 38 0b ea 8e 7d 95 43 70 52 0f b0 5f |"._.8...}.CpR.._| 00000110 ef 26 5a 52 a6 94 b4 69 89 e9 0e 4f f5 d8 60 1b |.&ZR...i...O..`.| 00000120 d3 6a fd 74 8d 19 ce 6a 72 f1 c1 96 f9 86 66 3b |.j.t...jr.....f;| 00000130 2b 38 b3 e3 76 4b fd 4a 82 3e f2 2c bc 4c 19 d7 |+8..vK.J.>.,.L..|
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 25 00:14:50 UTC 2023 - 7.3K bytes - Viewed (0) -
src/runtime/sys_windows_arm64.s
AND $~1, R3 LSL $3, R3 SUB R3, RSP // R4: size of stack arguments (n-8)*8 // R5: &args[8] // R6: loop counter, from 0 to (n-8)*8 // R7: scratch // R8: copy of RSP - (R2)(RSP) assembles as (R2)(ZR) SUB $8, R0, R4 LSL $3, R4 ADD $(8*8), R12, R5 MOVD $0, R6 MOVD RSP, R8 stackargs: MOVD (R6)(R5), R7 MOVD R7, (R6)(R8) ADD $8, R6 CMP R6, R4 BNE stackargs _8args:
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Sep 21 15:56:43 UTC 2023 - 6.8K bytes - Viewed (0) -
src/crypto/tls/testdata/Client-TLSv13-P256-ECDHE
00000230 ec 62 4b ba d1 94 98 e5 de 45 f4 92 22 79 9a 2e |.bK......E.."y..| 00000240 b4 12 a6 f8 ab 8a 52 c3 df f8 77 a9 71 8b ff d6 |......R...w.q...| 00000250 2b bc 47 0b 63 5b 0f cf f8 f1 86 7a 72 91 78 7b |+.G.c[.....zr.x{| 00000260 b8 52 74 96 40 4c 08 f3 ca 46 ef d9 b9 6d 7a dc |******@****.***.| 00000270 2c da f1 c2 c4 1f 19 38 84 cf 7d b7 5d f2 19 a7 |,......8..}.]...|
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 22:33:38 UTC 2024 - 7.1K bytes - Viewed (0) -
src/crypto/aes/asm_arm64.s
ks128Loop: VMOV R7, V2.S[0] WORD $0x4E030042 // TBL V3.B16, [V2.B16], V2.B16 AESE V0.B16, V2.B16 // Use AES to compute the SBOX EORW R13, R4 LSLW $1, R13 // Compute next Rcon ANDSW $0x100, R13, ZR CSELW NE, R14, R13, R13 // Fake modulo SUBS $1, R8 VMOV V2.S[0], R0 EORW R0, R4 EORW R4, R5 EORW R5, R6 EORW R6, R7 STPW.P (R4, R5), 8(R10) STPW.P (R6, R7), 8(R10) BNE ks128Loop
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 6.9K bytes - Viewed (0)