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Results 1 - 3 of 3 for xor (0.14 sec)
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src/cmd/asm/internal/asm/testdata/loong64enc3.s
OR $74565, R4, R5 // 5e020014de178d0385781500 OR $4097, R4 // 3e000014de07800384781500 OR $4097, R4, R5 // 3e000014de07800385781500 XOR $74565, R4 // 5e020014de178d0384f81500 XOR $74565, R4, R5 // 5e020014de178d0385f81500 XOR $4097, R4 // 3e000014de07800384f81500
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Sat May 14 23:57:43 GMT 2022 - 6.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/loong64enc2.s
OR $4096, R4 // 3e00001484781500 OR $-1, R4, R5 // 1efcbf0285781500 OR $-1, R4 // 1efcbf0284781500 XOR $65536, R4, R5 // 1e02001485f81500 XOR $4096, R4, R5 // 3e00001485f81500 XOR $65536, R4 // 1e02001484f81500 XOR $4096, R4 // 3e00001484f81500 XOR $-1, R4, R5 // 1efcbf0285f81500 XOR $-1, R4 // 1efcbf0284f81500 MOVH R4, R5 // 85c04000a5c04800 // relocation instructions
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Mon Apr 10 15:50:11 GMT 2023 - 3K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arm.go
if op == arm.AMRC { op1 = 1 } bits, ok := ParseARMCondition(cond) if !ok { return } offset = (0xe << 24) | // opcode (op1 << 20) | // MCR/MRC ((int64(bits) ^ arm.C_SCOND_XOR) << 28) | // scond ((x0 & 15) << 8) | //coprocessor number ((x1 & 7) << 21) | // coprocessor operation ((x2 & 15) << 12) | // ARM register ((x3 & 15) << 16) | // Crn ((x4 & 15) << 0) | // Crm
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Nov 18 17:59:44 GMT 2022 - 6.1K bytes - Viewed (0)