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src/cmd/asm/internal/asm/testdata/mips64.s
// // move immediate: macro for lui+or, addi, addis, and other combinations // // LMOVW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MOVW $1, R1 MOVV $1, R1 // LMOVW ximm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MOVW $1, R1 MOVW $foo(SB), R1 MOVV $1, R1 MOVV $foo(SB), R1 // // floating point operate // // LFCONV freg ',' freg // {
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Aug 08 12:17:12 GMT 2023 - 12.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
// // SWAP // // LTYPE9 cond reg ',' ireg ',' reg // { // outcode($1, $2, &$5, int32($3.Reg), &$7); // } STREX R1, (R2), R3 // STREX (R2), R1, R3 // // word // // LTYPEH comma ximm // { // outcode($1, Always, &nullgen, 0, &$3); // } WORD $1234 // // floating-point coprocessor // // LTYPEI cond freg ',' freg // { // outcode($1, $2, &$3, 0, &$5); // }
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Dec 15 20:51:01 GMT 2023 - 69K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/mips.s
// // move immediate: macro for lui+or, addi, addis, and other combinations // // LMOVW imm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MOVW $1, R1 MOVW $1, R1 // LMOVW ximm ',' rreg // { // outcode(int($1), &$2, 0, &$4); // } MOVW $1, R1 MOVW $foo(SB), R1 MOVW $1, R1 MOVW $foo(SB), R1 // // branch // // LBRA rel // {
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Aug 08 12:17:12 GMT 2023 - 6.7K bytes - Viewed (0)