VMINUB:         "vminub",
	VMINUH:         "vminuh",
	VMINUW:         "vminuw",
	VMLADDUHM:      "vmladduhm",
	VMRGHB:         "vmrghb",
	VMRGHH:         "vmrghh",
	VMRGHW:         "vmrghw",
	VMRGLB:         "vmrglb",
	VMRGLH:         "vmrglh",
	VMRGLW:         "vmrglw",
	VMSUMMBM:       "vmsummbm",
	VMSUMSHM:       "vmsumshm",
	VMSUMSHS:       "vmsumshs",
	VMSUMUBM:       "vmsumubm",

	VADDUWM V12, V26, V12

	VMRGEW V0, V1, V27
	VMRGEW V2, V3, V28

	VMRGOW V0, V1, V0
	VMRGOW V2, V3, V2

	VMRGEW V4, V5, V29
	VMRGEW V6, V7, V30

	XXPERMDI VS32, VS34, $0, VS33
	XXPERMDI VS32, VS34, $3, VS35
	XXPERMDI VS59, VS60, $0, VS32
	XXPERMDI VS59, VS60, $3, VS34

	VMRGOW V4, V5, V4
	VMRGOW V6, V7, V6

	VMRGEW V8, V9, V27
	VMRGEW V10, V11, V28

	"VSPLTISB",
	"VSPLTISH",
	"VSPLTISW",
	"VCIPH",
	"VCIPHER",
	"VCIPHERLAST",
	"VNCIPH",
	"VNCIPHER",
	"VNCIPHERLAST",
	"VSBOX",
	"VSHASIGMA",
	"VSHASIGMAW",
	"VSHASIGMAD",
	"VMRGEW",
	"VMRGOW",
	"VCLZLSBB",
	"VCTZLSBB",
	"LXV",
	"LXVL",
	"LXVLL",
	"LXVD2X",
	"LXVW4X",
	"LXVH8X",
	"LXVB16X",
	"LXVX",
	"LXVDSX",
	"STXV",
	"STXVL",
	"STXVLL",
	"STXVD2X",

	VSTM M0, M3, off(dst)

#define SHUFFLE(a, b, c, d, t, u, v, w) \
	VMRHF a, c, t \ // t = {a[0], c[0], a[1], c[1]}
	VMRHF b, d, u \ // u = {b[0], d[0], b[1], d[1]}
	VMRLF a, c, v \ // v = {a[2], c[2], a[3], c[3]}
	VMRLF b, d, w \ // w = {b[2], d[2], b[3], d[3]}
	VMRHF t, u, a \ // a = {a[0], b[0], c[0], d[0]}
	VMRLF t, u, b \ // b = {a[1], b[1], c[1], d[1]}
	VMRHF v, w, c \ // c = {a[2], b[2], c[2], d[2]}

	AVSPLTW
	AVSPLTISB
	AVSPLTISH
	AVSPLTISW
	AVCIPH
	AVCIPHER
	AVCIPHERLAST
	AVNCIPH
	AVNCIPHER
	AVNCIPHERLAST
	AVSBOX
	AVSHASIGMA
	AVSHASIGMAW
	AVSHASIGMAD
	AVMRGEW
	AVMRGOW
	AVCLZLSBB
	AVCTZLSBB

	/* VSX */
	ALXV
	ALXVL
	ALXVLL
	ALXVD2X
	ALXVW4X
	ALXVH8X
	ALXVB16X
	ALXVX
	ALXVDSX
	ASTXV
	ASTXVL
	ASTXVLL
	ASTXVD2X

//
//
// Vector multiply word
//
//	VMLF  x0, x1, out_low
//	VMLHF x0, x1, out_hi
#define VMULT(x1, x2, out_low, out_hi) \
	VMULEUW x1, x2, TMP1; \
	VMULOUW x1, x2, TMP2; \
	VMRGEW TMP1, TMP2, out_hi; \
	VMRGOW TMP1, TMP2, out_low

//
// Vector multiply add word
//
//	VMALF  x0, x1, y, out_low
//	VMALHF x0, x1, y, out_hi
#define VMULT_ADD(x1, x2, y, one, out_low, out_hi) \
	VMULEUW  y, one, TMP2; \

			opset(ASTVX, r0)
			opset(ASTVXL, r0)

		case AVAND: /* vand, vandc, vnand */
			opset(AVAND, r0)
			opset(AVANDC, r0)
			opset(AVNAND, r0)

		case AVMRGOW: /* vmrgew, vmrgow */
			opset(AVMRGEW, r0)

		case AVOR: /* vor, vorc, vxor, vnor, veqv */
			opset(AVOR, r0)
			opset(AVORC, r0)
			opset(AVXOR, r0)
			opset(AVNOR, r0)
			opset(AVEQV, r0)

5z0m7ObnTUUN0DH8TqHMe8I7zshEhHC80RVVKvM8x3Td9Tbu9k5u2UFw/L7v/74eqj+y/DshvTi3eNGr9notGcvLr/zRAsnWlzfX/GAWOHtGpwcyhwwWJTZnuFZBcNyDsy0G085jgtc/C9hPLKBjvwMPPvmFIFv1TEYmdHENAh1SoDAM1tnLgMSRQVzsNiHCcXQqeXZnstdYmzP/1yQwH9SgqGsaDWG7z8kaXUqVF9D4Vnw3j6PmW1y+MGHw+94XQjK4acrlDobo/SL1F9/xwaNxvjqnakgRI6l+HBa40PCa+FkEvHRcKqaATaLaMI+grf3dQ7qHMSIvAD+FGO6+9dsMxifl3z0aqYaffn7UplR2W+rChyi2kSbjkIeahP4876p7BYMLV/JZit2ljgVojrUznoV2zOprlLdZano9nrzrLWeGz0nqVre3r4doShpHf8TePaBVDqu0272+vOSWXUVyQ2PYfrHw44qOELCJx5IxfOJr2Ddr...

	XXLXOR VS1, VS2, VS3            // f06114d0
	XXSEL VS1, VS2, VS3, VS4        // f08110f0
	XXSEL VS33, VS34, VS35, VS36    // f08110ff
	XXSEL V1, V2, V3, V4            // f08110ff
	XXMRGHW VS1, VS2, VS3           // f0611090
	XXMRGLW VS1, VS2, VS3           // f0611190
	XXSPLTW VS1, $1, VS2            // f0410a90
	XXSPLTW VS33, $1, VS34          // f0410a93
	XXSPLTW V1, $1, V2              // f0410a93