VADDUWM V12, V26, V12

	VMRGEW V0, V1, V27
	VMRGEW V2, V3, V28

	VMRGOW V0, V1, V0
	VMRGOW V2, V3, V2

	VMRGEW V4, V5, V29
	VMRGEW V6, V7, V30

	XXPERMDI VS32, VS34, $0, VS33
	XXPERMDI VS32, VS34, $3, VS35
	XXPERMDI VS59, VS60, $0, VS32
	XXPERMDI VS59, VS60, $3, VS34

	VMRGOW V4, V5, V4
	VMRGOW V6, V7, V6

	VMRGEW V8, V9, V27
	VMRGEW V10, V11, V28

	"VSPLTISB",
	"VSPLTISH",
	"VSPLTISW",
	"VCIPH",
	"VCIPHER",
	"VCIPHERLAST",
	"VNCIPH",
	"VNCIPHER",
	"VNCIPHERLAST",
	"VSBOX",
	"VSHASIGMA",
	"VSHASIGMAW",
	"VSHASIGMAD",
	"VMRGEW",
	"VMRGOW",
	"VCLZLSBB",
	"VCTZLSBB",
	"LXV",
	"LXVL",
	"LXVLL",
	"LXVD2X",
	"LXVW4X",
	"LXVH8X",
	"LXVB16X",
	"LXVX",
	"LXVDSX",
	"STXV",
	"STXVL",
	"STXVLL",
	"STXVD2X",

//
//
// Vector multiply word
//
//	VMLF  x0, x1, out_low
//	VMLHF x0, x1, out_hi
#define VMULT(x1, x2, out_low, out_hi) \
	VMULEUW x1, x2, TMP1; \
	VMULOUW x1, x2, TMP2; \
	VMRGEW TMP1, TMP2, out_hi; \
	VMRGOW TMP1, TMP2, out_low

//
// Vector multiply add word
//
//	VMALF  x0, x1, y, out_low
//	VMALHF x0, x1, y, out_hi
#define VMULT_ADD(x1, x2, y, one, out_low, out_hi) \
	VMULEUW  y, one, TMP2; \

	VMINUB:         "vminub",
	VMINUH:         "vminuh",
	VMINUW:         "vminuw",
	VMLADDUHM:      "vmladduhm",
	VMRGHB:         "vmrghb",
	VMRGHH:         "vmrghh",
	VMRGHW:         "vmrghw",
	VMRGLB:         "vmrglb",
	VMRGLH:         "vmrglh",
	VMRGLW:         "vmrglw",
	VMSUMMBM:       "vmsummbm",
	VMSUMSHM:       "vmsumshm",
	VMSUMSHS:       "vmsumshs",
	VMSUMUBM:       "vmsumubm",

			opset(ASTVX, r0)
			opset(ASTVXL, r0)

		case AVAND: /* vand, vandc, vnand */
			opset(AVAND, r0)
			opset(AVANDC, r0)
			opset(AVNAND, r0)

		case AVMRGOW: /* vmrgew, vmrgow */
			opset(AVMRGEW, r0)

		case AVOR: /* vor, vorc, vxor, vnor, veqv */
			opset(AVOR, r0)
			opset(AVORC, r0)
			opset(AVXOR, r0)
			opset(AVNOR, r0)
			opset(AVEQV, r0)

	AVSPLTW
	AVSPLTISB
	AVSPLTISH
	AVSPLTISW
	AVCIPH
	AVCIPHER
	AVCIPHERLAST
	AVNCIPH
	AVNCIPHER
	AVNCIPHERLAST
	AVSBOX
	AVSHASIGMA
	AVSHASIGMAW
	AVSHASIGMAD
	AVMRGEW
	AVMRGOW
	AVCLZLSBB
	AVCTZLSBB

	/* VSX */
	ALXV
	ALXVL
	ALXVLL
	ALXVD2X
	ALXVW4X
	ALXVH8X
	ALXVB16X
	ALXVX
	ALXVDSX
	ASTXV
	ASTXVL
	ASTXVLL
	ASTXVD2X

00000110  6d b4 56 c4 23 56 5d 3c  fc 6d 69 ce eb e2 9c 30  |m.V.#V]<.mi....0|
00000120  da 34 39 32 80 a7 26 d6  e2 11 33 a5 c1 5d 75 07  |.492..&...3..]u.|
00000130  f5 f6 98 9e f2 26 49 96  52 fb 56 6d 34 67 45 15  |.....&I.R.Vm4gE.|
00000140  97 0d 0d 5e 7e 63 6b 42  0e 6f 2c 3b 11 06 d5 a4  |...^~ckB.o,;....|
00000150  00 92 2d 39 62 ea f4 28  04 ee e4 f4 78 f4 d2 72  |..-9b..(....x..r|

// already exists at package scope and is available at sym.Def.(*ir.Name).Type().
// Local types (which may have the same name as a package-level type) are
// distinguished by their vargen, which is embedded in their symbol name.
type Type struct {
	// extra contains extra etype-specific fields.
	// As an optimization, those etype-specific structs which contain exactly

those at the other end, by reason that they cross in the intermediate
white; namely, their ends, which verge towards [Greek: Ux], will be red
and yellow on that side next the center, and blue and violet on the
other side. But their other ends which verge from [Greek: Ux], will on
the contrary be blue and violet on that side towards the center, and on
the other side red and yellow.

And the Colours at one end of every Arc must be in a contrary order to those at the other end, by reason that they cross in the intermediate white; namely, their ends, which verge towards [Greek: Ux], will be red and yellow on that side next the center, and blue and violet on the other side. But their other ends which verge from [Greek: Ux], will on the contrary be blue and violet on that side towards the center, and on the other side red and yellow. Now as all these things follow from the properties...