ok = true
					}
				} else if prefix == 0xC5 || prefix == 0xC4 {
					if vex == prefix {
						ok = true
					}
				} else if vex != 0 && (prefix == 0x0F || prefix == 0x0F38 || prefix == 0x0F3A ||
					prefix == 0x66 || prefix == 0xF2 || prefix == 0xF3) {
					var vexM, vexP Prefix
					if vex == 0xC5 {
						vexM = 1 // 2 byte vex always implies 0F
						vexP = inst.Prefix[vexIndex+1]
					} else {

	// e.g. setting the xsavedisable boot option on Windows 10.
	X86.HasOSXSAVE = isSet(ecx1, cpuid_OSXSAVE)

	// The FMA instruction set extension only has VEX prefixed instructions.
	// VEX prefixed instructions require OSXSAVE to be enabled.
	// See Intel 64 and IA-32 Architecture Software Developer’s Manual Volume 2
	// Section 2.4 "AVX and SSE Instruction Exception Specification"

	PrefixREXB      Prefix = 0x01 // extension bit B (r/m field in modrm or base field in sib)
	PrefixVEX2Bytes Prefix = 0xC5 // Short form of vex prefix
	PrefixVEX3Bytes Prefix = 0xC4 // Long form of vex prefix
)

// IsREX reports whether p is a REX prefix byte.
func (p Prefix) IsREX() bool {
	return p&0xF0 == PrefixREX
}

func (p Prefix) IsVEX() bool {

	RxrEvex = 1 << 4 // AVX512 extension to REX.R/VEX.R
	Rxw     = 1 << 3 // =1, 64-bit operand size
	Rxr     = 1 << 2 // extend modrm reg
	Rxx     = 1 << 1 // extend sib index
	Rxb     = 1 << 0 // extend modrm r/m, sib base, or opcode reg
)

const (
	// Encoding for VEX prefix in tables.
	// The P, L, and W fields are chosen to match
	// their eventual locations in the VEX prefix bytes.

	VADDPD X0, X1, K0, X2           // ERROR "invalid instruction"
	VADDPD Y0, Y1, K0, Y2           // ERROR "invalid instruction"
	VADDPD Z0, Z1, K0, Z2           // ERROR "invalid instruction"
	// VEX-encoded VSIB can't use High-16 registers as index (unlike EVEX).
	// TODO(quasilyte): improve error message (#21860).
	VPGATHERQQ X2, (BP)(X20*2), X3  // ERROR "invalid instruction"

//	VEX.NDS.256.66.0F.WIG EF /r
//
// Produce this optab entry:
//
//	{AVPXOR, yvex_xy3, Pavx, opBytes{vex128|vex66|vex0F|vexWIG, 0xEF, vex256|vex66|vex0F|vexWIG, 0xEF}}
//
// VEX requires at least 2 bytes inside opBytes:
//	- VEX prefixes (vex-prefixed constants)
//	- Opcode byte
//
// EVEX instructions extend VEX form variety:
//	VTHING zmm2/m512, zmmV, zmm1    -- implicit K0 (merging)

	VMOVQ X20, -15(R11)(CX*1) // 62c1fd087ea40bf1ffffff or 62c1fd08d6a40bf1ffffff
	VMOVQ X20, (SP)(AX*2)     // 62e1fd087e2444 or 62e1fd08d62444
	// VMOVHPD: overlapping VEX and EVEX variants.
	VMOVHPD (AX), X5, X5             // c5d11628 or c4e1d11628 or 62f1d5281628 or 62f1d5481628
	VMOVHPD 7(DX), X5, X5            // c5d1166a07 or 62f1d52816aa07000000 or 62f1d54816aa07000000