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Results 1 - 2 of 2 for variant (0.21 sec)

  1. src/cmd/asm/internal/asm/testdata/amd64enc_extra.s

    	VMOVQ X20, -15(R11)(CX*1) // 62c1fd087ea40bf1ffffff or 62c1fd08d6a40bf1ffffff
    	VMOVQ X20, (SP)(AX*2)     // 62e1fd087e2444 or 62e1fd08d62444
    	// VMOVHPD: overlapping VEX and EVEX variants.
    	VMOVHPD (AX), X5, X5             // c5d11628 or c4e1d11628 or 62f1d5281628 or 62f1d5481628
    	VMOVHPD 7(DX), X5, X5            // c5d1166a07 or 62f1d52816aa07000000 or 62f1d54816aa07000000
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Apr 11 18:32:50 GMT 2023
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  2. src/cmd/asm/internal/asm/testdata/amd64error.s

    	VPGATHERDQ (BP)(X15*2), K1, Y15 // ERROR "index and destination registers should be distinct"
    	VPGATHERDQ (BP)(Y20*2), K1, Z20 // ERROR "index and destination registers should be distinct"
    	// Instructions without EVEX variant can't use High-16 registers.
    	VADDSUBPD X20, X1, X2           // ERROR "invalid instruction"
    	VADDSUBPS X0, X20, X2           // ERROR "invalid instruction"
    	// Use of K0 for write mask (Yknot0).
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Wed Jun 14 00:03:57 GMT 2023
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