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Results 1 - 10 of 41 for sradi (0.3 sec)

  1. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/plan9.go

    	MULLDO:    "MULLDV",
    	MULLDOCC:  "MULLDVCC",
    	DIVDO:     "DIVDV",
    	DIVDOCC:   "DIVDVCC",
    	DIVDUO:    "DIVDUV",
    	DIVDUOCC:  "DIVDUVCC",
    	ADDI:      "ADD",
    	MULLI:     "MULLD",
    	SRADI:     "SRAD",
    	STBCXCC:   "STBCCC",
    	STWCXCC:   "STWCCC",
    	STDCXCC:   "STDCCC",
    	LI:        "MOVD",
    	LBZ:       "MOVBZ", STB: "MOVB",
    	LBZU: "MOVBZU", STBU: "MOVBU",
    	LHZ: "MOVHZ", LHA: "MOVH", STH: "MOVH",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 22 17:16:14 UTC 2022
    - 10.9K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/ppc64/doc.go

    correct result, and the assembler does not add extra checking.
    
    Examples:
    
    	SRAD $8,R3,R4		=>	sradi r4,r3,8
    	SRD $8,R3,R4		=>	rldicl r4,r3,56,8
    	SLD $8,R3,R4		=>	rldicr r4,r3,8,55
    	SRAW $16,R4,R5		=>	srawi r5,r4,16
    	SRW $40,R4,R5		=>	rlwinm r5,r4,0,0,31
    	SLW $12,R4,R5		=>	rlwinm r5,r4,12,0,19
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Apr 21 16:47:45 UTC 2023
    - 11.3K bytes
    - Viewed (0)
  3. src/cmd/vendor/golang.org/x/arch/ppc64/ppc64asm/tables.go

    	RLDIMICC:       "rldimi.",
    	SC:             "sc",
    	SLBIA:          "slbia",
    	SLBIE:          "slbie",
    	SLD:            "sld",
    	SLDCC:          "sld.",
    	SRAD:           "srad",
    	SRADCC:         "srad.",
    	SRADI:          "sradi",
    	SRADICC:        "sradi.",
    	SRD:            "srd",
    	SRDCC:          "srd.",
    	STD:            "std",
    	STDCXCC:        "stdcx.",
    	STDU:           "stdu",
    	STDUX:          "stdux",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 22 17:16:14 UTC 2022
    - 334.7K bytes
    - Viewed (0)
  4. test/codegen/shift.go

    	return uint64(v) >> 8
    }
    
    func rshConst64x64(v int64) int64 {
    	// ppc64x:"SRAD"
    	// riscv64:"SRAI\t",-"OR",-"SLTIU"
    	return v >> uint64(33)
    }
    
    func rshConst64x64Overflow32(v int32) int64 {
    	// riscv64:"SRAIW",-"SLLI",-"SRAI\t"
    	return int64(v) >> 32
    }
    
    func rshConst64x64Overflow16(v int16) int64 {
    	// riscv64:"SLLI","SRAI",-"SRAIW"
    	return int64(v) >> 16
    }
    
    func rshConst64x64Overflow8(v int8) int64 {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue May 21 18:53:43 UTC 2024
    - 12.7K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/RISCV64latelower.rules

    // license that can be found in the LICENSE file.
    
    // Fold constant shift with extension.
    (SRAI [c] (MOVBreg  x)) && c <   8 => (SRAI [56+c] (SLLI <typ.Int64> [56] x))
    (SRAI [c] (MOVHreg  x)) && c <  16 => (SRAI [48+c] (SLLI <typ.Int64> [48] x))
    (SRAI [c] (MOVWreg  x)) && c <  32 => (SRAI [32+c] (SLLI <typ.Int64> [32] x))
    (SRLI [c] (MOVBUreg x)) && c <   8 => (SRLI [56+c] (SLLI <typ.UInt64> [56] x))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Oct 24 03:45:10 UTC 2022
    - 980 bytes
    - Viewed (0)
  6. src/cmd/compile/internal/ssa/rewriteRISCV64latelower.go

    		return true
    	}
    	return false
    }
    func rewriteValueRISCV64latelower_OpRISCV64SRAI(v *Value) bool {
    	v_0 := v.Args[0]
    	b := v.Block
    	typ := &b.Func.Config.Types
    	// match: (SRAI [c] (MOVBreg x))
    	// cond: c < 8
    	// result: (SRAI [56+c] (SLLI <typ.Int64> [56] x))
    	for {
    		c := auxIntToInt64(v.AuxInt)
    		if v_0.Op != OpRISCV64MOVBreg {
    			break
    		}
    		x := v_0.Args[0]
    		if !(c < 8) {
    			break
    		}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Jan 19 22:42:34 UTC 2023
    - 5.1K bytes
    - Viewed (0)
  7. src/math/asinh_s390x.s

    TEXT	·asinhAsm(SB), NOSPLIT, $0-16
    	FMOVD	x+0(FP), F0
    	MOVD	$·asinhrodataL18<>+0(SB), R9
    	LGDR	F0, R12
    	WORD	$0xC0293FDF	//iilf	%r2,1071644671
    	BYTE	$0xFF
    	BYTE	$0xFF
    	SRAD	$32, R12
    	WORD	$0xB917001C	//llgtr	%r1,%r12
    	MOVW	R1, R6
    	MOVW	R2, R7
    	CMPBLE	R6, R7, L2
    	WORD	$0xC0295FEF	//iilf	%r2,1609564159
    	BYTE	$0xFF
    	BYTE	$0xFF
    	MOVW	R2, R7
    	CMPBLE	R6, R7, L14
    L3:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 16 15:34:41 UTC 2019
    - 5.7K bytes
    - Viewed (0)
  8. src/math/acosh_s390x.s

    TEXT	·acoshAsm(SB), NOSPLIT, $0-16
    	FMOVD	x+0(FP), F0
    	MOVD	$·acoshrodataL11<>+0(SB), R9
    	LGDR	F0, R1
    	WORD	$0xC0295FEF	//iilf	%r2,1609564159
    	BYTE	$0xFF
    	BYTE	$0xFF
    	SRAD	$32, R1
    	CMPW	R1, R2
    	BGT	L2
    	WORD	$0xC0293FEF	//iilf	%r2,1072693247
    	BYTE	$0xFF
    	BYTE	$0xFF
    	CMPW	R1, R2
    	BGT	L10
    L3:
    	WFCEDBS	V0, V0, V2
    	BVS	L1
    	FMOVD	112(R9), F0
    L1:
    	FMOVD	F0, ret+8(FP)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 16 15:34:41 UTC 2019
    - 4.3K bytes
    - Viewed (0)
  9. src/cmd/asm/internal/asm/testdata/riscv64error.s

    	SRLI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
    	SRAI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
    	RORI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
    	SLLI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
    	SRLI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
    	SRAI	$-1, X5, X6			// ERROR "immediate out of range 0 to 63"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sun Apr 07 03:32:27 UTC 2024
    - 2.8K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/_gen/RISCV64.rules

    (SRAI <t> [x] (MOVWreg  y)) && x >= 0 && x <= 31 => (SRAIW <t> [int64(x)] y)
    (SRLI <t> [x] (MOVWUreg y)) && x >= 0 && x <= 31 => (SRLIW <t> [int64(x)] y)
    
    // Replace right shifts that exceed size of signed type.
    (SRAI <t> [x] (MOVBreg y)) && x >=  8 => (SRAI  [63] (SLLI <t> [56] y))
    (SRAI <t> [x] (MOVHreg y)) && x >= 16 => (SRAI  [63] (SLLI <t> [48] y))
    (SRAI <t> [x] (MOVWreg y)) && x >= 32 => (SRAIW [31] y)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu Mar 07 14:57:07 UTC 2024
    - 40.3K bytes
    - Viewed (0)
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