}
}

func sarx64(x, y int64) int64 {
	// amd64/v3:"SARXQ"
	return x >> y
}

func sarx32(x, y int32) int32 {
	// amd64/v3:"SARXL"
	return x >> y
}

func sarx64_load(x []int64, i int) int64 {
	// amd64/v3: `SARXQ\t[A-Z]+[0-9]*, \([A-Z]+[0-9]*\)\([A-Z]+[0-9]*\*8\), [A-Z]+[0-9]*`
	s := x[i] >> (i & 63)
	// amd64/v3: `SARXQ\t[A-Z]+[0-9]*, 8\([A-Z]+[0-9]*\)\([A-Z]+[0-9]*\*8\), [A-Z]+[0-9]*`

			break
		}
		v.copyOf(x)
		return true
	}
	return false
}
func rewriteValueAMD64latelower_OpAMD64SARL(v *Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SARL x y)
	// cond: buildcfg.GOAMD64 >= 3
	// result: (SARXL x y)
	for {
		x := v_0
		y := v_1
		if !(buildcfg.GOAMD64 >= 3) {
			break
		}
		v.reset(OpAMD64SARXL)
		v.AddArg2(x, y)
		return true
	}
	return false
}

	"RORXQ",
	"ROUNDPD",
	"ROUNDPS",
	"ROUNDSD",
	"ROUNDSS",
	"RSM",
	"RSQRTPS",
	"RSQRTSS",
	"SAHF",
	"SALB",
	"SALL",
	"SALQ",
	"SALW",
	"SARB",
	"SARL",
	"SARQ",
	"SARW",
	"SARXL",
	"SARXQ",
	"SBBB",
	"SBBL",
	"SBBQ",
	"SBBW",
	"SCASB",
	"SCASL",
	"SCASQ",
	"SCASW",
	"SETCC",
	"SETCS",
	"SETEQ",
	"SETGE",
	"SETGT",
	"SETHI",

		"andnq", "andnl", "andn",
		"blsiq", "blsil", "blsi",
		"blsmskq", "blsmskl", "blsmsk",
		"blsrq", "blsrl", "blsr",
		"tzcntq", "tzcntl", "tzcnt",
	},
	"bmi2": {
		"sarxq", "sarxl", "sarx",
		"shlxq", "shlxl", "shlx",
		"shrxq", "shrxl", "shrx",
	},
	"sse41": {
		"roundsd",
		"pinsrq", "pinsrl", "pinsrd", "pinsrb", "pinsr",
		"pextrq", "pextrl", "pextrd", "pextrb", "pextr",

		// CPUID feature: BMI2.
		{name: "SARXQ", argLength: 2, reg: gp21, asm: "SARXQ"}, // signed arg0 >> arg1, shift amount is mod 64
		{name: "SARXL", argLength: 2, reg: gp21, asm: "SARXL"}, // signed int32(arg0) >> arg1, shift amount is mod 32
		{name: "SHLXQ", argLength: 2, reg: gp21, asm: "SHLXQ"}, // arg0 << arg1, shift amount is mod 64

	SARB $7, R11                            // 41c0fb07
	SARXL R9, (BX), DX                      // c4e232f713
	SARXL R9, (R11), DX                     // c4c232f713
	SARXL R9, DX, DX                        // c4e232f7d2
	SARXL R9, R11, DX                       // c4c232f7d3
	SARXL R9, (BX), R11                     // c46232f71b
	SARXL R9, (R11), R11                    // c44232f71b
	SARXL R9, DX, R11                       // c46232f7da

// See comments in ARM64latelower.rules...

# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
# KIND, either express or implied.  See the License for the
# specific language governing permissions and limitations
# under the License.

((SHLL|SHRL|SARL) x (ADDQconst [c] y)) && c & 31 == 0  => ((SHLL|SHRL|SARL) x y)
((SHLL|SHRL|SARL) x (NEGQ <t> (ADDQconst [c] y))) && c & 31 == 0  => ((SHLL|SHRL|SARL) x (NEGQ <t> y))
((SHLL|SHRL|SARL) x (ANDQconst [c] y)) && c & 31 == 31 => ((SHLL|SHRL|SARL) x y)
((SHLL|SHRL|SARL) x (NEGQ <t> (ANDQconst [c] y))) && c & 31 == 31 => ((SHLL|SHRL|SARL) x (NEGQ <t> y))

	ARORXL
	ARORXQ
	AROUNDPD
	AROUNDPS
	AROUNDSD
	AROUNDSS
	ARSM
	ARSQRTPS
	ARSQRTSS
	ASAHF
	ASALB
	ASALL
	ASALQ
	ASALW
	ASARB
	ASARL
	ASARQ
	ASARW
	ASARXL
	ASARXQ
	ASBBB
	ASBBL
	ASBBQ
	ASBBW
	ASCASB
	ASCASL
	ASCASQ
	ASCASW
	ASETCC
	ASETCS
	ASETEQ
	ASETGE
	ASETGT
	ASETHI
	ASETLE
	ASETLS
	ASETLT
	ASETMI