VPMADD52HUQ -7(DI)(R8*4), X31, K1, X18             // 62a28501b59487f9ffffff
	VPMADD52HUQ X7, X3, K1, X18                        // 62e2e509b5d7
	VPMADD52HUQ X0, X3, K1, X18                        // 62e2e509b5d0
	VPMADD52HUQ 17(SP)(BP*2), X3, K1, X18              // 62e2e509b5946c11000000
	VPMADD52HUQ -7(DI)(R8*4), X3, K1, X18              // 62a2e509b59487f9ffffff

	VPERMB X0, X2, K1, X23                             // 62e26d098df8
	VPERMB 7(SI)(DI*4), X2, K1, X23                    // 62e26d098dbcbe07000000
	VPERMB -7(DI)(R8*2), X2, K1, X23                   // 62a26d098dbc47f9ffffff
	VPERMB X26, X9, K1, X23                            // 628235098dfa
	VPERMB X19, X9, K1, X23                            // 62a235098dfb

	VPDPWSSDS Y31, Y1, K1, Y9                          // 6212752953cf
	VPDPWSSDS (R8), Y1, K1, Y9                         // 625275295308
	VPDPWSSDS 15(DX)(BX*2), Y1, K1, Y9                 // 62727529538c5a0f000000
	VPDPWSSDS Y0, Y9, K1, Y9                           // 6272352953c8
	VPDPWSSDS Y19, Y9, K1, Y9                          // 6232352953cb

	VGF2P8AFFINEQB $82, X19, X0, K1, X15               // 6233fd09cefb52
	VGF2P8AFFINEQB $82, 17(SP)(BP*2), X0, K1, X15      // 6273fd09cebc6c1100000052
	VGF2P8AFFINEQB $82, -7(DI)(R8*4), X0, K1, X15      // 6233fd09cebc87f9ffffff52
	VGF2P8AFFINEQB $82, X22, X28, K1, X15              // 62339d01cefe52
	VGF2P8AFFINEQB $82, X7, X28, K1, X15               // 62739d01ceff52

	VEXP2PS Z20, K1, Z1                                // 62b27d49c8cc
	VEXP2PS Z9, K1, Z1                                 // 62d27d49c8c9
	VEXP2PS 99(R15)(R15*4), K1, Z1                     // 62927d49c88cbf63000000
	VEXP2PS 15(DX), K1, Z1                             // 62f27d49c88a0f000000
	VEXP2PS Z20, K1, Z9                                // 62327d49c8cc
	VEXP2PS Z9, K1, Z9                                 // 62527d49c8c9

	VPLZCNTQ Y14, K1, Y22                              // 62c2fd2944f6
	VPLZCNTQ 15(R8)(R14*4), K1, Y22                    // 6282fd2944b4b00f000000
	VPLZCNTQ -7(CX)(DX*4), K1, Y22                     // 62e2fd2944b491f9ffffff
	VPLZCNTQ Y12, K1, Y13                              // 6252fd2944ec
	VPLZCNTQ Y1, K1, Y13                               // 6272fd2944e9

	VPSHUFBITQMB Z3, Z6, K7, K1                        // 62f24d4f8fcb
	VPSHUFBITQMB Z21, Z6, K7, K1                       // 62b24d4f8fcd
	VPSHUFBITQMB -15(R14)(R15*1), Z6, K7, K1           // 62924d4f8f8c3ef1ffffff
	VPSHUFBITQMB -15(BX), Z6, K7, K1                   // 62f24d4f8f8bf1ffffff
	VPSHUFBITQMB Z3, Z25, K7, K1                       // 62f235478fcb
	VPSHUFBITQMB Z21, Z25, K7, K1                      // 62b235478fcd

//
// For 386/AMD64 register list specifies 4VNNIW-style multi-source operand.
// For range of 4 elements, Intel manual uses "+3" notation, for example:
//
//	VP4DPWSSDS zmm1{k1}{z}, zmm2+3, m128
//
// Given asm line:
//
//	VP4DPWSSDS Z5, [Z10-Z13], (AX)
//
// zmm2 is Z10, and Z13 is the only valid value for it (Z10+3).
// Only simple ranges are accepted, like [Z0-Z3].
//