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  1. src/cmd/asm/internal/asm/testdata/s390x.s

    	VSUMQG	V19, V20, V21           // e75340003e67
    	VSUMB	V7, V8, V9              // e79780000064
    	VSUMH	V22, V23, V24           // e78670001e64
    
    	RET
    	RET	foo(SB)
    
    TEXT main·init(SB),DUPOK|NOSPLIT,$0 // TEXT main.init(SB), DUPOK|NOSPLIT, $0
    	RET
    
    TEXT main·main(SB),DUPOK|NOSPLIT,$0 // TEXT main.main(SB), DUPOK|NOSPLIT, $0
    	BL      main·foo(SB)    // CALL main.foo(SB)
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Wed Nov 22 03:55:32 GMT 2023
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  2. src/cmd/asm/internal/asm/testdata/mips64.s

    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	ADDD	F1, F2
    
    //	LFADD freg ',' freg ',' freg
    //	{
    //		outcode(int($1), &$2, int($4.Reg), &$6);
    //	}
    	ADDD	F1, F2, F3
    
    //	LFCMP freg ',' freg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	CMPEQD	F1, F2
    
    
    //
    // WORD
    //
    	WORD	$1	// 00000001
    	NOOP		// 00000000
    	SYNC		// 0000000f
    
    //
    // NOP
    //
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    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Aug 08 12:17:12 GMT 2023
    - 12.4K bytes
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  3. src/cmd/asm/internal/asm/testdata/amd64enc.s

    	INSERTPS $7, X2, X11                    // 66440f3a21da07
    	INSERTPS $7, X11, X11                   // 66450f3a21db07
    	INSW                                    // 666d
    	//TODO: INT $3                          // cc
    	INT $7                                  // cd07
    	INVD                                    // 0f08
    	INVLPG (BX)                             // 0f013b
    	INVLPG (R11)                            // 410f013b
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Oct 08 21:38:44 GMT 2021
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  4. src/cmd/asm/internal/asm/testdata/386.s

    TEXT foo(SB), DUPOK|NOSPLIT, $0
    
    // LTYPE1 nonrem	{ outcode(int($1), &$2); }
    	SETCC	AX
    	SETCC	foo+4(SB)
    
    // LTYPE2 rimnon	{ outcode(int($1), &$2); }
    	DIVB	AX
    	DIVB	foo+4(SB)
    	PUSHL	$foo+4(SB)
    	POPL		AX
    
    // LTYPE3 rimrem	{ outcode(int($1), &$2); }
    	SUBB	$1, AX
    	SUBB	$1, foo+4(SB)
    	SUBB	BX, AX
    	SUBB	BX, foo+4(SB)
    
    // LTYPE4 remrim	{ outcode(int($1), &$2); }
    	CMPB	AX, $1
    	CMPB	foo+4(SB), $4
    	CMPB	BX, AX
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Apr 09 18:57:21 GMT 2019
    - 2K bytes
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  5. .github/ISSUE_TEMPLATE/03-gopls.yml

        attributes:
          label: "What did you do?"
          description: "If possible, provide a recipe for reproducing the error. A complete runnable program is good. A link on [go.dev/play](https://go.dev/play) is better. A failing unit test is the best."
        validations:
          required: true
      - type: textarea
        id: actual-behavior
        attributes:
          label: "What did you see happen?"
        validations:
          required: true
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Thu Jan 04 23:31:17 GMT 2024
    - 1.8K bytes
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  6. src/cmd/asm/internal/asm/testdata/amd64.s

    #include "../../../../../runtime/textflag.h"
    
    TEXT	foo(SB), DUPOK|NOSPLIT, $0
    
    // LTYPE1 nonrem	{ outcode($1, &$2); }
    	NEGQ	R11
    	NEGQ	4(R11)
    	NEGQ	foo+4(SB)
    
    // LTYPE2 rimnon	{ outcode($1, &$2); }
    	INT	$4
    	DIVB	R11
    	DIVB	4(R11)
    	DIVB	foo+4(SB)
    
    // LTYPE3 rimrem	{ outcode($1, &$2); }
    	SUBQ $4, DI
    	SUBQ R11, DI
    	SUBQ 4(R11), DI
    	SUBQ foo+4(SB), DI
    	SUBQ $4, 8(R12)
    	SUBQ R11, 8(R12)
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    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Apr 09 18:57:21 GMT 2019
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  7. src/cmd/asm/internal/asm/testdata/mips.s

    	//	LADDW rreg ',' sreg ',' rreg
    	//	{
    	//		outcode(int($1), &$2, int($4), &$6);
    	//	}
    	ADD	R1, R2, R3
    
    	//	LADDW imm ',' sreg ',' rreg
    	//	{
    	//		outcode(int($1), &$2, int($4), &$6);
    	//	}
    	ADD	$1, R2, R3
    
    	//	LADDW rreg ',' rreg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	ADD	R1, R2
    
    	//	LADDW imm ',' rreg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	ADD	$4, R1
    
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Aug 08 12:17:12 GMT 2023
    - 6.7K bytes
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