const setInt32 = (addr, v) => {
				this.mem.setUint32(addr + 0, v, true);
			}

			const getInt64 = (addr) => {
				const low = this.mem.getUint32(addr + 0, true);
				const high = this.mem.getInt32(addr + 4, true);
				return low + high * 4294967296;
			}

			const loadValue = (addr) => {
				const f = this.mem.getFloat64(addr, true);
				if (f === 0) {
					return undefined;
				}
				if (!isNaN(f)) {

		f.walk(&n.X, ctxExpr, visit)
		f.walk(&n.Index, ctxExpr, visit)
	case *ast.SliceExpr:
		f.walk(&n.X, ctxExpr, visit)
		if n.Low != nil {
			f.walk(&n.Low, ctxExpr, visit)
		}
		if n.High != nil {
			f.walk(&n.High, ctxExpr, visit)
		}
		if n.Max != nil {
			f.walk(&n.Max, ctxExpr, visit)
		}
	case *ast.TypeAssertExpr:
		f.walk(&n.X, ctxExpr, visit)
		f.walk(&n.Type, ctxType, visit)

	err = syscall.Mprotect(b[:pagesize], syscall.PROT_NONE)
	if err != nil {
		t.Fatalf("mprotect low failed %s\n", err)
	}
	err = syscall.Mprotect(b[2*pagesize:], syscall.PROT_NONE)
	if err != nil {
		t.Fatalf("mprotect high failed %s\n", err)
	}
	return b[pagesize : 2*pagesize]
}

func TestEqualNearPageBoundary(t *testing.T) {
	t.Parallel()
	b := dangerousSlice(t)
	for i := range b {
		b[i] = 'A'
	}

index defaults to zero; a missing <code>high</code> index defaults to the length of the
sliced operand:
</p>

<pre>
a[2:]  // same as a[2 : len(a)]
a[:3]  // same as a[0 : 3]
a[:]   // same as a[0 : len(a)]
</pre>

<p>
If <code>a</code> is a pointer to an array, <code>a[low : high]</code> is shorthand for
<code>(*a)[low : high]</code>.
</p>

<p>

	VPGATHERDQ (BP)(X15*2), K1, Y15 // ERROR "index and destination registers should be distinct"
	VPGATHERDQ (BP)(Y20*2), K1, Z20 // ERROR "index and destination registers should be distinct"
	// Instructions without EVEX variant can't use High-16 registers.
	VADDSUBPD X20, X1, X2           // ERROR "invalid instruction"
	VADDSUBPS X0, X20, X2           // ERROR "invalid instruction"
	// Use of K0 for write mask (Yknot0).

	{"[k3-k6]", "register list: bad low register in `[k3`"},
	{"[X0]", "register list: expected '-' after `[X0`, found ']'"},
	{"[X0-]", "register list: bad high register in `[X0-]`"},
	{"[X0-x]", "register list: bad high register in `[X0-x`"},
	{"[X0-X1-X2]", "register list: expected ']' after `[X0-X1`, found '-'"},
	{"[X0,X3]", "register list: expected '-' after `[X0`, found ','"},

	VEXTRACTPS $-1, X1, AX       // c4e37917c8ff
	VPEXTRB $-1, X1, AX          // c4e37914c8ff
	VPEXTRD $-1, X1, AX          // c4e37916c8ff
	VPEXTRQ $-1, X1, AX          // c4e3f916c8ff
	// EVEX: High-16 X registers.
	VADDPD X30, X1, X0          // 6291f50858c6
	VADDPD X2, X29, X0          // 62f1950058c2
	VADDPD X30, X29, X0         // 6291950058c6
	VADDPD X2, X1, X28          // 6261f50858e2

	case arm.ACMPF, arm.ACMPD:
		return true
	}
	return false
}

// ARMMRCOffset implements the peculiar encoding of the MRC and MCR instructions.
// The difference between MRC and MCR is represented by a bit high in the word, not
// in the usual way by the opcode itself. Asm must use AMRC for both instructions, so
// we return the opcode for MRC so that asm doesn't need to import obj/arm.

	{"3/0", "division by zero"},
	{"(1<<63)/0", "divide of value with high bit set"},
	{"3%0", "modulo by zero"},
	{"(1<<63)%0", "modulo of value with high bit set"},
	{"3<<-4", "negative left shift count"},
	{"3<<(1<<63)", "negative left shift count"},
	{"3>>-4", "negative right shift count"},
	{"3>>(1<<63)", "negative right shift count"},
	{"(1<<63)>>2", "right shift of value with high bit set"},
	{"(1<<62)>>2", ""},

pkg syscall (netbsd-arm64-cgo), const IP_PORTRANGE_DEFAULT = 0
pkg syscall (netbsd-arm64-cgo), const IP_PORTRANGE_DEFAULT ideal-int
pkg syscall (netbsd-arm64-cgo), const IP_PORTRANGE_HIGH = 1
pkg syscall (netbsd-arm64-cgo), const IP_PORTRANGE_HIGH ideal-int
pkg syscall (netbsd-arm64-cgo), const IP_PORTRANGE ideal-int
pkg syscall (netbsd-arm64-cgo), const IP_PORTRANGE_LOW = 2
pkg syscall (netbsd-arm64-cgo), const IP_PORTRANGE_LOW ideal-int