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doc/go_mem.html
go f() } </pre> <p> calling <code>hello</code> will print <code>"hello, world"</code> at some point in the future (perhaps after <code>hello</code> has returned). </p> <h3 id="goexit">Goroutine destruction</h3> <p> The exit of a goroutine is not guaranteed to be synchronized before any event in the program. For example, in this program: </p> <pre> var a string func hello() {
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Tue Aug 05 15:41:37 GMT 2025 - 26.6K bytes - Click Count (0) -
compat/maven-artifact/src/main/java/org/apache/maven/artifact/versioning/Restriction.java
Created: Sun Dec 28 03:35:09 GMT 2025 - Last Modified: Fri Jun 06 14:28:57 GMT 2025 - 4.3K bytes - Click Count (0) -
compat/maven-artifact/src/test/java/org/apache/maven/artifact/versioning/VersionRangeTest.java
List<Restriction> restrictions = range.getRestrictions(); assertEquals(1, restrictions.size(), CHECK_NUM_RESTRICTIONS); Restriction restriction = restrictions.get(0); assertNull(restriction.getLowerBound(), CHECK_LOWER_BOUND); assertFalse(restriction.isLowerBoundInclusive(), CHECK_LOWER_BOUND_INCLUSIVE); assertEquals("1.0", restriction.getUpperBound().toString(), CHECK_UPPER_BOUND);
Created: Sun Dec 28 03:35:09 GMT 2025 - Last Modified: Sun Mar 30 23:08:36 GMT 2025 - 44.1K bytes - Click Count (0) -
src/cmd/asm/internal/asm/testdata/amd64error.s
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Wed Jun 14 00:03:57 GMT 2023 - 8.9K bytes - Click Count (0) -
.github/bot_config.yml
*TensorFlow release binaries version 1.6 and higher are prebuilt with AVX instruction sets.* Therefore on any CPU that does not have these instruction sets, either CPU or GPU version of TF will fail to load. Apparently, your CPU model does not support AVX instruction sets. You can still use TensorFlow with the alternatives given below: * Try Google Colab to use TensorFlow.Created: Tue Dec 30 12:39:10 GMT 2025 - Last Modified: Mon Jun 30 16:38:59 GMT 2025 - 4K bytes - Click Count (1) -
compat/maven-artifact/src/main/java/org/apache/maven/artifact/versioning/VersionRange.java
} private List<Restriction> intersection(List<Restriction> r1, List<Restriction> r2) { List<Restriction> restrictions = new ArrayList<>(r1.size() + r2.size()); Iterator<Restriction> i1 = r1.iterator(); Iterator<Restriction> i2 = r2.iterator(); Restriction res1 = i1.next(); Restriction res2 = i2.next(); boolean done = false;Created: Sun Dec 28 03:35:09 GMT 2025 - Last Modified: Wed Jul 23 17:27:08 GMT 2025 - 19K bytes - Click Count (0) -
src/cmd/asm/internal/arch/riscv64.go
} return false } // IsRISCV64VTypeI reports whether op is a vtype immediate instruction that // requires special handling. func IsRISCV64VTypeI(op obj.As) bool { return op == riscv.AVSETVLI || op == riscv.AVSETIVLI } // IsRISCV64CSRO reports whether the op is an instruction that uses // CSR symbolic names and whether that instruction expects a register // or an immediate source operand.
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Fri Sep 12 08:12:45 GMT 2025 - 2.8K bytes - Click Count (0) -
compat/maven-compat/src/main/java/org/apache/maven/artifact/repository/metadata/ArtifactRepositoryMetadata.java
} VersionRange range = artifact.getVersionRange(); if (range != null) { for (Restriction restriction : range.getRestrictions()) { if (isSnapshot(restriction.getLowerBound()) || isSnapshot(restriction.getUpperBound())) { return RELEASE_OR_SNAPSHOT; } } } return RELEASE; }Created: Sun Dec 28 03:35:09 GMT 2025 - Last Modified: Fri Jun 06 14:28:57 GMT 2025 - 3.6K bytes - Click Count (0) -
doc/asm.html
Instead, the compiler operates on a kind of semi-abstract instruction set, and instruction selection occurs partly after code generation. The assembler works on the semi-abstract form, so when you see an instruction like <code>MOV</code> what the toolchain actually generates for that operation might not be a move instruction at all, perhaps a clear or load. Or it might correspond exactly to the machine instruction with that name.
Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Fri Nov 14 19:09:46 GMT 2025 - 36.5K bytes - Click Count (0) -
src/cmd/asm/internal/asm/line_test.go
{"VADDPD.RZ_SAE.SAE X0, X1, X2", `bad suffix combination`}, // BSWAP on 16-bit registers is undefined. See #29167, {"BSWAPW DX", `unrecognized instruction`}, {"BSWAPW R11", `unrecognized instruction`}, }) } func testBadInstParser(t *testing.T, goarch string, tests []badInstTest) { for i, test := range tests { arch, ctxt := setArch(goarch)Created: Tue Dec 30 11:13:12 GMT 2025 - Last Modified: Tue Aug 29 07:48:38 GMT 2023 - 1.9K bytes - Click Count (0)