}
	return false
}

type sys uint8

const (
	sys_AT sys = iota
	sys_DC
	sys_IC
	sys_TLBI
	sys_SYS
)

func sys_op_4(op1, crn, crm, op2 uint32) sys {
	sysInst := sysInstFields{uint8(op1), uint8(crn), uint8(crm), uint8(op2)}
	return sysInst.getType()
}

func is_zero(x uint32) bool {
	return x == 0
}

func is_ones_n16(x uint32) bool {
	return x == 0xffff
}

		((int64(bits) ^ arm.C_SCOND_XOR) << 28) | // scond
		((x0 & 15) << 8) | //coprocessor number
		((x1 & 7) << 21) | // coprocessor operation
		((x2 & 15) << 12) | // ARM register
		((x3 & 15) << 16) | // Crn
		((x4 & 15) << 0) | // Crm
		((x5 & 7) << 5) | // coprocessor information
		(1 << 4) /* must be set */
	return offset, arm.AMRC, true
}

// IsARMMULA reports whether the op (as defined by an arm.A* constant) is

	VSn is used for vector-scalar registers. V0-V31 overlap with VS32-VS63. (0-63)
	CTR represents the count register.
	LR represents the link register.
	CR represents the condition register
	CRn represents a condition register field. (0-7)
	CRnLT represents CR bit 0 of CR field n. (0-7)
	CRnGT represents CR bit 1 of CR field n. (0-7)
	CRnEQ represents CR bit 2 of CR field n. (0-7)

		if (cond >> 1) == 7 {
			return nil
		}
		return Cond{uint8(cond), true}

	case arg_Cm:
		CRm := (x >> 8) & (1<<4 - 1)
		return Imm_c(CRm)

	case arg_Cn:
		CRn := (x >> 12) & (1<<4 - 1)
		return Imm_c(CRn)

	case arg_option_DMB_BO_system_CRm:
		CRm := (x >> 8) & (1<<4 - 1)
		return Imm_option(CRm)

	case arg_option_DSB_BO_system_CRm:
		CRm := (x >> 8) & (1<<4 - 1)

{"Name":"MRS","Bits":"1|1|0|1|0|1|0|1|0|0|1|1|o0|op1:3|CRn:4|CRm:4|op2:3|Rt:5","Arch":"System variant","Syntax":"MRS <Xt>, (<systemreg>|S<op0>_<op1>_<Cn>_<Cm>_<op2>)","Code":"","Alias":""},
{"Name":"MSR (immediate)","Bits":"1|1|0|1|0|1|0|1|0|0|0|0|0|op1:3|0|1|0|0|CRm:4|op2:3|1|1|1|1|1","Arch":"System variant","Syntax":"MSR <pstatefield>, #<imm>","Code":"","Alias":""},

//			(($2^C_SCOND_XOR) << 28) |		/* scond */
//			(($3 & 15) << 8) |	/* coprocessor number */
//			(($5 & 7) << 21) |	/* coprocessor operation */
//			(($7 & 15) << 12) |	/* arm register */
//			(($9 & 15) << 16) |	/* Crn */
//			(($11 & 15) << 0) |	/* Crm */
//			(($12 & 7) << 5) |	/* coprocessor information */
//			(1<<4));			/* must be set */
//		outcode(AMRC, Always, &nullgen, 0, &g);
//	}

func OPBLR(x uint32) uint32 {
	/* x=0, JMP; 1, CALL; 2, RET */
	return 0x6B<<25 | 0<<23 | x<<21 | 0x1F<<16 | 0<<10
}

func SYSOP(l uint32, op0 uint32, op1 uint32, crn uint32, crm uint32, op2 uint32, rt uint32) uint32 {
	return 0x354<<22 | l<<21 | op0<<19 | op1<<16 | crn&15<<12 | crm&15<<8 | op2<<5 | rt
}

func SYSHINT(x uint32) uint32 {
	return SYSOP(0, 0, 3, 2, 0, x, 0x1F)
}