result += "-" + r1.String() + r.a.String()
			}
		}
		result += "}"
	}
	return fmt.Sprintf("%s[%d]", result, r.index)
}

type sysOp struct {
	op          sysInstFields
	r           Reg
	hasOperand2 bool
}

func (s sysOp) isArg() {}

func (s sysOp) String() string {
	result := s.op.String()
	// If s.hasOperand2 is false, the value in the register
	// specified by s.r is ignored.

	case AMSR:
		return SYSOP(0, 0, 0, 4, 0, 0, 0x1F) /* MSR (immediate) */

	case AAT,
		ADC,
		AIC,
		ATLBI,
		ASYS:
		return SYSOP(0, 1, 0, 0, 0, 0, 0)

	case ASYSL:
		return SYSOP(1, 1, 0, 0, 0, 0, 0)

	case ATBZ:
		return 0x36 << 24

	case ATBNZ:
		return 0x37 << 24

	case ADSB:
		return SYSOP(0, 0, 3, 3, 0, 4, 0x1F)

	case ADMB:

	case Imm_prfop:
		if strings.Contains(a.String(), "#") {
			return fmt.Sprintf("$%d", a)
		}
	case sysOp:
		result := a.op.String()
		if a.r != 0 {
			result += ", " + plan9gpr(a.r)
		}
		return result
	}

	return strings.ToUpper(arg.String())
}

		attrs := sysInst.getAttrs()
		reg := int(x & 31)
		if !attrs.hasOperand2 {
			if reg == 31 {
				return sysOp{sysInst, 0, false}
			}
			// This instruction is undefined if the Rt field is not set to 31.
			return nil
		}
		return sysOp{sysInst, X0 + Reg(reg), true}

	case arg_Bt:
		return B0 + Reg(x&(1<<5-1))

	case arg_Dt:
		return D0 + Reg(x&(1<<5-1))