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Results 1 - 10 of 10 for asmKind (0.13 sec)

  1. src/cmd/vendor/golang.org/x/tools/go/analysis/passes/asmdecl/asmdecl.go

    	case asmSlice:
    		cc = append(cc, newComponent(suffix+"_base", asmKind(arch.ptrSize), "slice base", off, arch.ptrSize, suffix))
    		cc = append(cc, newComponent(suffix+"_len", asmKind(arch.intSize), "slice len", off+arch.ptrSize, arch.intSize, suffix))
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri May 03 02:38:00 UTC 2024
    - 22.8K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/x86/asm6.go

    			case Zm_r:
    				ab.Put1(byte(op))
    				ab.asmand(ctxt, cursym, p, &p.From, &p.To)
    
    			case Z_m_r:
    				ab.Put1(byte(op))
    				ab.asmand(ctxt, cursym, p, p.GetFrom3(), &p.To)
    
    			case Zm2_r:
    				ab.Put2(byte(op), o.op[z+1])
    				ab.asmand(ctxt, cursym, p, &p.From, &p.To)
    
    			case Zm_r_xm:
    				ab.mediaop(ctxt, o, op, int(yt.zoffset), z)
    				ab.asmand(ctxt, cursym, p, &p.From, &p.To)
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 15:44:14 UTC 2024
    - 146.9K bytes
    - Viewed (0)
  3. src/cmd/compile/internal/ssa/debug_lines_test.go

    	"reflect"
    	"regexp"
    	"runtime"
    	"sort"
    	"strconv"
    	"strings"
    	"testing"
    )
    
    // Matches lines in genssa output that are marked "isstmt", and the parenthesized plus-prefixed line number is a submatch
    var asmLine *regexp.Regexp = regexp.MustCompile(`^\s[vb]\d+\s+\d+\s\(\+(\d+)\)`)
    
    // this matches e.g.                            `   v123456789   000007   (+9876654310) MOVUPS	X15, ""..autotmp_2-32(SP)`
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Nov 21 20:24:52 UTC 2023
    - 8.4K bytes
    - Viewed (0)
  4. src/cmd/compile/internal/ssa/flags_test.go

    	}
    	coverage := map[flagConstant]bool{}
    	for _, x := range numbers {
    		for _, y := range numbers {
    			a := logicFlags64(x & y)
    			b := flagRegister2flagConstant(asmAndFlags(x, y), false)
    			if a != b {
    				t.Errorf("asmAnd diff: x=%x y=%x got=%s want=%s\n", x, y, a, b)
    			}
    			coverage[a] = true
    		}
    	}
    	if len(coverage) != 3 {
    		t.Errorf("coverage too small, got %d want 3", len(coverage))
    	}
    }
    
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Oct 04 19:36:17 UTC 2022
    - 2.5K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/riscv/cpu.go

    	AFCLASSS
    
    	// 12.3: Double-Precision Load and Store Instructions
    	AFLD
    	AFSD
    
    	// 12.4: Double-Precision Floating-Point Computational Instructions
    	AFADDD
    	AFSUBD
    	AFMULD
    	AFDIVD
    	AFMIND
    	AFMAXD
    	AFSQRTD
    	AFMADDD
    	AFMSUBD
    	AFNMADDD
    	AFNMSUBD
    
    	// 12.5: Double-Precision Floating-Point Conversion and Move Instructions
    	AFCVTWD
    	AFCVTLD
    	AFCVTDW
    	AFCVTDL
    	AFCVTWUD
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 13.1K bytes
    - Viewed (0)
  6. src/cmd/internal/obj/riscv/inst.go

    	case AFMAXD:
    		return &inst{0x53, 0x1, 0x0, 672, 0x15}
    	case AFMAXQ:
    		return &inst{0x53, 0x1, 0x0, 736, 0x17}
    	case AFMAXS:
    		return &inst{0x53, 0x1, 0x0, 640, 0x14}
    	case AFMIND:
    		return &inst{0x53, 0x0, 0x0, 672, 0x15}
    	case AFMINQ:
    		return &inst{0x53, 0x0, 0x0, 736, 0x17}
    	case AFMINS:
    		return &inst{0x53, 0x0, 0x0, 640, 0x14}
    	case AFMSUBD:
    		return &inst{0x47, 0x0, 0x0, 32, 0x1}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 13.9K bytes
    - Viewed (0)
  7. src/cmd/internal/obj/arm64/a.out.go

    	AFCVTZSS
    	AFCVTZSSW
    	AFCVTZUD
    	AFCVTZUDW
    	AFCVTZUS
    	AFCVTZUSW
    	AFDIVD
    	AFDIVS
    	AFLDPD
    	AFLDPQ
    	AFLDPS
    	AFMADDD
    	AFMADDS
    	AFMAXD
    	AFMAXNMD
    	AFMAXNMS
    	AFMAXS
    	AFMIND
    	AFMINNMD
    	AFMINNMS
    	AFMINS
    	AFMOVD
    	AFMOVQ
    	AFMOVS
    	AFMSUBD
    	AFMSUBS
    	AFMULD
    	AFMULS
    	AFNEGD
    	AFNEGS
    	AFNMADDD
    	AFNMADDS
    	AFNMSUBD
    	AFNMSUBS
    	AFNMULD
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Oct 18 17:56:30 UTC 2023
    - 18.1K bytes
    - Viewed (0)
  8. src/cmd/internal/obj/riscv/obj.go

    	AFADDD & obj.AMask:   rFFFEncoding,
    	AFSUBD & obj.AMask:   rFFFEncoding,
    	AFMULD & obj.AMask:   rFFFEncoding,
    	AFDIVD & obj.AMask:   rFFFEncoding,
    	AFMIND & obj.AMask:   rFFFEncoding,
    	AFMAXD & obj.AMask:   rFFFEncoding,
    	AFSQRTD & obj.AMask:  rFFFEncoding,
    	AFMADDD & obj.AMask:  rFFFFEncoding,
    	AFMSUBD & obj.AMask:  rFFFFEncoding,
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sun Apr 07 03:32:27 UTC 2024
    - 77K bytes
    - Viewed (0)
  9. src/cmd/internal/obj/arm64/asm7.go

    			oprangeset(AFMULS, t)
    			oprangeset(AFMULD, t)
    			oprangeset(AFNMULS, t)
    			oprangeset(AFNMULD, t)
    			oprangeset(AFDIVS, t)
    			oprangeset(AFMAXD, t)
    			oprangeset(AFMAXS, t)
    			oprangeset(AFMIND, t)
    			oprangeset(AFMINS, t)
    			oprangeset(AFMAXNMD, t)
    			oprangeset(AFMAXNMS, t)
    			oprangeset(AFMINNMD, t)
    			oprangeset(AFMINNMS, t)
    			oprangeset(AFDIVD, t)
    
    		case AFMSUBD:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 15:44:14 UTC 2024
    - 201.1K bytes
    - Viewed (0)
  10. src/cmd/compile/internal/ssa/opGen.go

    			},
    		},
    	},
    	{
    		name:   "FMIND",
    		argLen: 2,
    		asm:    arm64.AFMIND,
    		reg: regInfo{
    			inputs: []inputInfo{
    				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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