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Results 1 - 9 of 9 for AFADDD (0.14 sec)

  1. src/cmd/internal/obj/x86/aenum.go

    	ADECB
    	ADECL
    	ADECQ
    	ADECW
    	ADIVB
    	ADIVL
    	ADIVPD
    	ADIVPS
    	ADIVQ
    	ADIVSD
    	ADIVSS
    	ADIVW
    	ADPPD
    	ADPPS
    	AEMMS
    	AENTER
    	AEXTRACTPS
    	AF2XM1
    	AFABS
    	AFADDD
    	AFADDDP
    	AFADDF
    	AFADDL
    	AFADDW
    	AFBLD
    	AFBSTP
    	AFCHS
    	AFCLEX
    	AFCMOVB
    	AFCMOVBE
    	AFCMOVCC
    	AFCMOVCS
    	AFCMOVE
    	AFCMOVEQ
    	AFCMOVHI
    	AFCMOVLS
    	AFCMOVNB
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 11 18:32:50 UTC 2023
    - 16.3K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/riscv/cpu.go

    	AFCLASSS
    
    	// 12.3: Double-Precision Load and Store Instructions
    	AFLD
    	AFSD
    
    	// 12.4: Double-Precision Floating-Point Computational Instructions
    	AFADDD
    	AFSUBD
    	AFMULD
    	AFDIVD
    	AFMIND
    	AFMAXD
    	AFSQRTD
    	AFMADDD
    	AFMSUBD
    	AFNMADDD
    	AFNMSUBD
    
    	// 12.5: Double-Precision Floating-Point Conversion and Move Instructions
    	AFCVTWD
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 13.1K bytes
    - Viewed (0)
  3. src/cmd/internal/obj/riscv/inst.go

    		return &inst{0x3b, 0x5, 0x0, 32, 0x1}
    	case ADIVW:
    		return &inst{0x3b, 0x4, 0x0, 32, 0x1}
    	case AEBREAK:
    		return &inst{0x73, 0x0, 0x1, 1, 0x0}
    	case AECALL:
    		return &inst{0x73, 0x0, 0x0, 0, 0x0}
    	case AFADDD:
    		return &inst{0x53, 0x0, 0x0, 32, 0x1}
    	case AFADDQ:
    		return &inst{0x53, 0x0, 0x0, 96, 0x3}
    	case AFADDS:
    		return &inst{0x53, 0x0, 0x0, 0, 0x0}
    	case AFCLASSD:
    		return &inst{0x53, 0x1, 0x0, -480, 0x71}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 20 14:19:33 UTC 2024
    - 13.9K bytes
    - Viewed (0)
  4. src/cmd/internal/obj/arm64/a.out.go

    	ACSINVW
    	ACSNEG
    	ACSNEGW
    	ADC
    	ADCPS1
    	ADCPS2
    	ADCPS3
    	ADMB
    	ADRPS
    	ADSB
    	ADWORD
    	AEON
    	AEONW
    	AEOR
    	AEORW
    	AERET
    	AEXTR
    	AEXTRW
    	AFABSD
    	AFABSS
    	AFADDD
    	AFADDS
    	AFCCMPD
    	AFCCMPED
    	AFCCMPES
    	AFCCMPS
    	AFCMPD
    	AFCMPED
    	AFCMPES
    	AFCMPS
    	AFCSELD
    	AFCSELS
    	AFCVTDH
    	AFCVTDS
    	AFCVTHD
    	AFCVTHS
    	AFCVTSD
    	AFCVTSH
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Oct 18 17:56:30 UTC 2023
    - 18.1K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/x86/obj6.go

    				if p.To.Type == obj.TYPE_REG && REG_X0 <= p.To.Reg && p.To.Reg <= REG_X15 {
    					p.As = AXORPS
    					p.From = p.To
    					break
    				}
    			}
    		}
    		fallthrough
    
    	case AFMOVD,
    		AFADDD,
    		AFSUBD,
    		AFSUBRD,
    		AFMULD,
    		AFDIVD,
    		AFDIVRD,
    		AFCOMD,
    		AFCOMDP,
    		AADDSD,
    		ASUBSD,
    		AMULSD,
    		ADIVSD,
    		ACOMISD,
    		AUCOMISD:
    		if p.From.Type == obj.TYPE_FCONST {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Sep 08 18:36:45 UTC 2023
    - 40.9K bytes
    - Viewed (0)
  6. src/cmd/internal/obj/riscv/obj.go

    	// 12.3: Double-Precision Load and Store Instructions
    	AFLD & obj.AMask: iFEncoding,
    	AFSD & obj.AMask: sFEncoding,
    
    	// 12.4: Double-Precision Floating-Point Computational Instructions
    	AFADDD & obj.AMask:   rFFFEncoding,
    	AFSUBD & obj.AMask:   rFFFEncoding,
    	AFMULD & obj.AMask:   rFFFEncoding,
    	AFDIVD & obj.AMask:   rFFFEncoding,
    	AFMIND & obj.AMask:   rFFFEncoding,
    	AFMAXD & obj.AMask:   rFFFEncoding,
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Sun Apr 07 03:32:27 UTC 2024
    - 77K bytes
    - Viewed (0)
  7. src/cmd/internal/obj/arm64/asm7.go

    			oprangeset(AHLT, t)
    			oprangeset(ASMC, t)
    			oprangeset(ABRK, t)
    			oprangeset(ADCPS1, t)
    			oprangeset(ADCPS2, t)
    			oprangeset(ADCPS3, t)
    
    		case AFADDS:
    			oprangeset(AFADDD, t)
    			oprangeset(AFSUBS, t)
    			oprangeset(AFSUBD, t)
    			oprangeset(AFMULS, t)
    			oprangeset(AFMULD, t)
    			oprangeset(AFNMULS, t)
    			oprangeset(AFNMULD, t)
    			oprangeset(AFDIVS, t)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 15:44:14 UTC 2024
    - 201.1K bytes
    - Viewed (0)
  8. src/cmd/internal/obj/x86/asm6.go

    	{AFUCOMPP, ycompp, Px, opBytes{0xda, 13}},
    	{AFADDDP, ycompp, Px, opBytes{0xde, 00}},
    	{AFADDW, yfmvx, Px, opBytes{0xde, 00}},
    	{AFADDL, yfmvx, Px, opBytes{0xda, 00}},
    	{AFADDF, yfmvx, Px, opBytes{0xd8, 00}},
    	{AFADDD, yfadd, Px, opBytes{0xdc, 00, 0xd8, 00, 0xdc, 00}},
    	{AFMULDP, ycompp, Px, opBytes{0xde, 01}},
    	{AFMULW, yfmvx, Px, opBytes{0xde, 01}},
    	{AFMULL, yfmvx, Px, opBytes{0xda, 01}},
    	{AFMULF, yfmvx, Px, opBytes{0xd8, 01}},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed May 15 15:44:14 UTC 2024
    - 146.9K bytes
    - Viewed (0)
  9. src/cmd/compile/internal/ssa/opGen.go

    			},
    		},
    	},
    	{
    		name:        "FADDD",
    		argLen:      2,
    		commutative: true,
    		asm:         arm64.AFADDD,
    		reg: regInfo{
    			inputs: []inputInfo{
    				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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