// 2.4: Integer Computational Instructions

	ADDI	$2047, X5				// 9382f27f
	ADDI	$-2048, X5				// 93820280
	ADDI	$2048, X5				// 9382024093820240
	ADDI	$-2049, X5				// 938202c09382f2bf
	ADDI	$4094, X5				// 9382f27f9382f27f
	ADDI	$-4096, X5				// 9382028093820280
	ADDI	$4095, X5				// b71f00009b8fffffb382f201
	ADDI	$-4097, X5				// b7ffffff9b8fffffb382f201
	ADDI	$2047, X5, X6				// 1383f27f
	ADDI	$-2048, X5, X6				// 13830280

	//	}
	SLL	$4, R1, R2

	//	LSHW imm ',' rreg
	//	{
	//		outcode(int($1), &$2, 0, &$4);
	//	}
	SLL	$4, R1

	//
	// move immediate: macro for lui+or, addi, addis, and other combinations
	//
	//	LMOVW imm ',' rreg
	//	{
	//		outcode(int($1), &$2, 0, &$4);
	//	}
	MOVW	$1, R1
	MOVW	$1, R1

	//	LMOVW ximm ',' rreg
	//	{

//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	AND	$11, R17, R7	// 3227000b
	XOR	$341, R1, R23	// 38370155
	OR	$254, R25, R13	// 372d00fe
//
// move immediate: macro for lui+or, addi, addis, and other combinations
//
//	LMOVW imm ',' rreg
//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	MOVW	$1, R1
	MOVV	$1, R1

//	LMOVW ximm ',' rreg
//	{
//		outcode(int($1), &$2, 0, &$4);

	ADDW	(R5), R6              // 5a605000
	ADDW	4095(R7), R8          // 5a807fff
	ADDW	-1(R1), R2            // e3201fffff5a
	ADDW	4096(R3), R4          // e3403000015a
	ADDE	4096(R3), R4          // e34030000188
	ADDE	4096(R3)(R2*1), R4    // e34230000188
	ADDE	524288(R3)(R4*1), R5  // c0a10008000041aa4000e35a30000088
	MULLD	(R1)(R2*1), R3        // e3321000000c
	MULLW	(R3)(R4*1), R5        // 71543000

	//TODO: this compiles to add r5,r6,r0. It should be addi r5,r6,0.
	//      this is OK since r0 == $0, but the latter is preferred.
	ADD $0, R6, R5             	// 7ca60214

        //TODO: the assembler rewrites these into ADDIS $19, R5, Rx and ADD $-10617, Rx, Rx, but the test only sees the first ADDIS
	ADD $1234567, R5                // 3ca50013 or 0600001238a5d687