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src/cmd/asm/internal/asm/testdata/ppc64_p10.s
XVF32GERPP VS1, VS2, A1 // ec8110d0 XVF64GER VS2, VS1, A1 // ec8209d8 XVF64GERNN VS2, VS1, A1 // ec820fd0 XVF64GERNP VS2, VS1, A1 // ec820bd0 XVF64GERPN VS2, VS1, A1 // ec820dd0 XVF64GERPP VS2, VS1, A1 // ec8209d0 XVI16GER2 VS1, VS2, A1 // ec811258 XVI16GER2PP VS1, VS2, A1 // ec811358
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Thu Mar 23 20:52:57 GMT 2023 - 14.3K bytes - Viewed (0) -
src/cmd/asm/internal/asm/operand_test.go
{"-24(RSP)", "-24(RSP)"}, {"$24(RSP)", "$24(RSP)"}, {"-32(RSP)", "-32(RSP)"}, {"$48", "$48"}, {"$(-64*1024)(R7)", "$-65536(R7)"}, {"$(8-1)", "$7"}, {"a+0(FP)", "a(FP)"}, {"a1+8(FP)", "a1+8(FP)"}, {"·AddInt32(SB)", `pkg.AddInt32(SB)`}, {"runtime·divWVW(SB)", "runtime.divWVW(SB)"}, {"$argframe+0(FP)", "$argframe(FP)"}, {"$asmcgocall<>(SB)", "$asmcgocall<>(SB)"}, {"EQ", "EQ"}, {"F29", "F29"},
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Aug 29 18:31:05 GMT 2023 - 23.9K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arch.go
register["T0"] = riscv.REG_T0 register["T1"] = riscv.REG_T1 register["T2"] = riscv.REG_T2 register["S0"] = riscv.REG_S0 register["S1"] = riscv.REG_S1 register["A0"] = riscv.REG_A0 register["A1"] = riscv.REG_A1 register["A2"] = riscv.REG_A2 register["A3"] = riscv.REG_A3 register["A4"] = riscv.REG_A4 register["A5"] = riscv.REG_A5 register["A6"] = riscv.REG_A6 register["A7"] = riscv.REG_A7
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Mar 21 06:51:28 GMT 2023 - 21.3K bytes - Viewed (0) -
src/archive/zip/reader_test.go
0000110 08 d1 1f 8f 5a 9e 96 ee 45 cf a4 84 4e 4b e8 50 0000120 a7 13 d9 06 de 52 81 97 36 b2 d7 b8 fc 2b 5f 55 0000130 23 1f 32 59 cf 30 27 fb e2 8a b9 de 45 dd 63 9c 0000140 4b b5 8b 96 4c 7a 62 62 cc a1 a7 cf fa f1 fe dd 0000150 54 62 11 bf 36 78 b3 c7 b1 b5 f2 61 4d 4e dd 66 0000160 32 2e e6 70 34 5f f4 c9 e6 6c 43 6f da 6b c6 c3 0000170 09 2c ce 09 57 7f d2 7e b4 23 ba 7c 1b 99 bc 22
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Mar 27 18:23:49 GMT 2024 - 55.3K bytes - Viewed (0) -
doc/go1.17_spec.html
HTML - Registered: Tue May 07 11:14:38 GMT 2024 - Last Modified: Thu Apr 11 20:22:45 GMT 2024 - 211.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64dynlinkerror.s
// license that can be found in the LICENSE file. // Test to make sure that if we use R15 after it is clobbered by // a global variable access while dynamic linking, we get an error. // See issue 43661. TEXT ·a1(SB), 0, $0-0 CMPL runtime·writeBarrier(SB), $0 MOVL $0, R15 RET TEXT ·a2(SB), 0, $0-0 CMPL runtime·writeBarrier(SB), $0 MOVQ $0, R15 RET TEXT ·a3(SB), 0, $0-0 CMPL runtime·writeBarrier(SB), $0
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Mar 15 20:45:41 GMT 2023 - 4.8K bytes - Viewed (0) -
doc/go_spec.html
HTML - Registered: Tue May 07 11:14:38 GMT 2024 - Last Modified: Thu May 02 22:43:51 GMT 2024 - 279.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/asm.go
// passed RestArgs/AddRestSource if a[1].Type == obj.TYPE_REG { prog.Reg = p.getRegister(prog, op, &a[1]) prog.AddRestSource(a[2]) } else { // Don't set prog.Reg if a1 isn't a reg arg. prog.AddRestSourceArgs([]obj.Addr{a[1], a[2]}) } break } if p.arch.Family == sys.RISCV64 { prog.From = a[0] prog.Reg = p.getRegister(prog, op, &a[1])
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Feb 21 14:34:57 GMT 2024 - 25.3K bytes - Viewed (0)