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Results 1 - 10 of 19 for Y6 (0.41 sec)
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src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
VPGATHERDQ Y0, 664(X4*8), Y6 // c4e2fd9034e598020000 VPGATHERDQ Y0, 8(X14*1), Y6 // c4a2fd90343508000000 VPGATHERDQ Y0, -8(X14*1), Y6 // c4a2fd903435f8ffffff VPGATHERDQ Y0, 0(X14*1), Y6 // c4a2fd90343500000000 VPGATHERDQ Y0, 664(X14*1), Y6 // c4a2fd90343598020000 VPGATHERDQ Y0, 8(X14*8), Y6 // c4a2fd9034f508000000 VPGATHERDQ Y0, -8(X14*8), Y6 // c4a2fd9034f5f8ffffff
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 11 18:32:50 UTC 2023 - 57.6K bytes - Viewed (0) -
src/image/jpeg/idct.go
y3 = (y1 + w2mw6*y3) >> 3 y1 = y4 + y6 y4 -= y6 y6 = y5 + y7 y5 -= y7 // Stage 3. y7 = y8 + y3 y8 -= y3 y3 = y0 + y2 y0 -= y2 y2 = (r2*(y4+y5) + 128) >> 8 y4 = (r2*(y4-y5) + 128) >> 8 // Stage 4. s[8*0] = (y7 + y1) >> 14 s[8*1] = (y3 + y2) >> 14 s[8*2] = (y0 + y4) >> 14 s[8*3] = (y8 + y6) >> 14 s[8*4] = (y8 - y6) >> 14 s[8*5] = (y0 - y4) >> 14
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Apr 02 23:18:37 UTC 2019 - 5K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/avx512enc/avx512_vbmi2.s
VPSHLDQ $121, Y6, Y6, K5, Y6 // 62f3cd2d71f679 VPSHLDQ $121, (BX), Y6, K5, Y6 // 62f3cd2d713379 VPSHLDQ $121, -17(BP)(SI*1), Y6, K5, Y6 // 62f3cd2d71b435efffffff79 VPSHLDQ $121, Y19, Y11, K5, Y6 // 62b3a52d71f379 VPSHLDQ $121, Y7, Y11, K5, Y6 // 62f3a52d71f779
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue May 22 14:57:15 UTC 2018 - 97.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/avx512enc/avx512_vnni.s
VPDPBUSDS Y23, Y3, K2, Y6 // 62b2652a51f7 VPDPBUSDS (BX), Y3, K2, Y6 // 62f2652a5133 VPDPBUSDS -17(BP)(SI*1), Y3, K2, Y6 // 62f2652a51b435efffffff VPDPBUSDS Y28, Y8, K2, Y6 // 62923d2a51f4 VPDPBUSDS Y1, Y8, K2, Y6 // 62f23d2a51f1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue May 22 14:57:15 UTC 2018 - 27.5K bytes - Viewed (0) -
src/internal/types/testdata/check/init1.go
var y5 = x5 type T5 struct{} func (T5) m() int { _ = y5 return 0 } // issue 4847 // simplified test case var x6 = f6 var y6 /* ERROR "initialization cycle" */ = f6 func f6() { _ = y6 } // full test case type ( E int S int ) type matcher func(s *S) E func matchList(s *S) E { return matcher(matchAnyFn)(s) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Jan 17 19:54:25 UTC 2023 - 1.5K bytes - Viewed (0) -
src/crypto/sha512/sha512block_amd64.s
ORQ R12, DI ADDQ R14, R9 ADDQ R15, BX ADDQ R15, R9 ADDQ DI, R9 VPSRLQ $19, Y6, Y3 VPSLLQ $(64-19), Y6, Y1 VPOR Y1, Y3, Y3 VPXOR Y3, Y8, Y8 VPSRLQ $61, Y6, Y3 VPSLLQ $(64-61), Y6, Y1 VPOR Y1, Y3, Y3 VPXOR Y3, Y8, Y8 VPADDQ Y8, Y0, Y2 VPBLENDD $0xF0, Y2, Y6, Y6 MOVQ R9, DI RORXQ $41, BX, R13 RORXQ $18, BX, R14 ADDQ 3*8+frame_YFER(SP), DX
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Mar 04 17:29:44 UTC 2024 - 27K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/avx512enc/avx512dq.s
VORPS Y12, Y6, K7, Y6 // 62d14c2f56f4 VORPS -7(CX)(DX*1), Y6, K7, Y6 // 62f14c2f56b411f9ffffff VORPS -15(R14)(R15*4), Y6, K7, Y6 // 62914c2f56b4bef1ffffff VORPS Y11, Y26, K7, Y6 // 62d12c2756f3 VORPS Y26, Y26, K7, Y6 // 62912c2756f2
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue May 22 14:57:15 UTC 2018 - 194.8K bytes - Viewed (0) -
src/math/big/arith_arm.s
L6: MOVW.P 4(R2), R6 ORR R6<<R4, R7 MOVW.P R7, 4(R1) MOVW R6>>R3, R7 E6: TEQ R1, R5 BNE L6 MOVW R7, 0(R1) RET Y6: // copy loop, because shift 0 == shift 32 MOVW.P 4(R2), R6 MOVW.P R6, 4(R1) TEQ R1, R5 BNE Y6 X6: MOVW $0, R1 MOVW R1, c+28(FP) RET // func mulAddVWW(z, x []Word, y, r Word) (c Word) TEXT ·mulAddVWW(SB),NOSPLIT,$0 MOVW $0, R0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Oct 19 23:33:27 UTC 2023 - 4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64error.s
VPGATHERDQ Y2, (BP)(AX*2), Y1 // ERROR "invalid instruction" VPGATHERDQ Y5, 664(DX*8), Y6 // ERROR "invalid instruction" VPGATHERDQ Y5, (DX), Y0 // ERROR "invalid instruction" // VM/X rejects Y index register. VPGATHERDQ Y5, 664(Y14*8), Y6 // ERROR "invalid instruction" VPGATHERQQ X2, (BP)(Y7*2), X1 // ERROR "invalid instruction" // VM/Y rejects X index register.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Jun 14 00:03:57 UTC 2023 - 8.9K bytes - Viewed (0) -
src/internal/bytealg/equal_amd64.s
PCALIGN $16 hugeloop_avx2: CMPQ BX, $64 JB bigloop_avx2 VMOVDQU (SI), Y0 VMOVDQU (DI), Y1 VMOVDQU 32(SI), Y2 VMOVDQU 32(DI), Y3 VPCMPEQB Y1, Y0, Y4 VPCMPEQB Y2, Y3, Y5 VPAND Y4, Y5, Y6 VPMOVMSKB Y6, DX ADDQ $64, SI ADDQ $64, DI SUBQ $64, BX CMPL DX, $0xffffffff JEQ hugeloop_avx2 VZEROUPPER XORQ AX, AX // return 0 RET bigloop_avx2: VZEROUPPER
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Nov 17 16:34:40 UTC 2023 - 2.8K bytes - Viewed (0)