VAG	V3, V4, V4              // e743400030f3
	VAQ	V3, V4, V4              // e743400040f3
	VAB	V1, V2                  // e721200000f3
	VAH	V1, V2                  // e721200010f3
	VAF	V1, V2                  // e721200020f3
	VAG	V1, V2                  // e721200030f3
	VAQ	V1, V2                  // e721200040f3
	VSB	V3, V4, V4              // e744300000f7
	VSH	V3, V4, V4              // e744300010f7

	VPMULL2 V2.D2, V1.D2, V4.Q1                                 // 24e0e24e
	VPMULL V2.B8, V1.B8, V3.H8                                  // 23e0220e
	VPMULL2 V2.B16, V1.B16, V4.H8                               // 24e0224e
	VRBIT V10.B16, V21.B16                                      // 5559606e
	VREV32 V2.H8, V1.H8                                         // 4108606e
	VREV16 V2.B8, V1.B8                                         // 4118200e

	{"VS56", "VS56"},
	{"VS57", "VS57"},
	{"VS58", "VS58"},
	{"VS59", "VS59"},
	{"VS60", "VS60"},
	{"VS61", "VS61"},
	{"VS62", "VS62"},
	{"VS63", "VS63"},
	{"V0", "V0"},
	{"V1", "V1"},
	{"V2", "V2"},
	{"V3", "V3"},
	{"V4", "V4"},
	{"V5", "V5"},
	{"V6", "V6"},
	{"V7", "V7"},
	{"V8", "V8"},
	{"V9", "V9"},
	{"V10", "V10"},
	{"V11", "V11"},
	{"V12", "V12"},
	{"V13", "V13"},

constant. It can do this by reading object files. If cgo has decided
that t1 is a type, v2 and v3 are variables or functions, and i4, i5
are integer constants, u6 is an unsigned integer constant, and f7 and f8
are float constants, and s9 and s10 are string constants, it generates:

	<preamble>
	__typeof__(t1) *__cgo__1;
	__typeof__(v2) *__cgo__2;
	__typeof__(v3) *__cgo__3;
	__typeof__(i4) *__cgo__4;

	VDIVESD V1, V2, V3                      // 106113cb
	VDIVESQ V1, V2, V3                      // 1061130b
	VDIVESW V1, V2, V3                      // 1061138b
	VDIVEUD V1, V2, V3                      // 106112cb
	VDIVEUQ V1, V2, V3                      // 1061120b
	VDIVEUW V1, V2, V3                      // 1061128b
	VDIVSD V1, V2, V3                       // 106111cb

	VPMULL2	V1.H4, V2.H4, V3.Q1                              // ERROR "operand mismatch"
	VPMULL2	V1.D1, V2.D1, V3.Q1                              // ERROR "operand mismatch"
	VPMULL2	V1.B8, V2.B8, V3.H8                              // ERROR "operand mismatch"
	VEXT	$8, V1.B16, V2.B8, V2.B16                        // ERROR "invalid arrangement"
	VEXT	$8, V1.H8, V2.H8, V2.H8                          // ERROR "invalid arrangement"

</p>

<p>
If a vector instruction takes a length or an index as an argument then it will be the
first argument.
For example, <code>VLEIF</code> <code>$1,</code> <code>$16,</code> <code>V2</code> will load
the value sixteen into index one of <code>V2</code>.
Care should be taken when using vector instructions to ensure that they are available at
runtime.
To use vector instructions a machine must have both the vector facility (bit 129 in the

	}
}

// registerList parses an ARM or ARM64 register list expression, a list of
// registers in []. There may be comma-separated ranges or individual
// registers, as in [R1,R3-R5] or [V1.S4, V2.S4, V3.S4, V4.S4].
// For ARM, only R0 through R15 may appear.
// For ARM64, V0 through V31 with arrangement may appear.
//
// For 386/AMD64 register list specifies 4VNNIW-style multi-source operand.