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Results 1 - 5 of 5 for UMOD (0.07 sec)
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src/crypto/internal/boring/build-goboring.sh
} u128 __udivti3(u128 x, u128 y) { return div(x, y, 0); } EOF extra="" case $GOARCH in amd64) cp umod-amd64.s umod.s clang -c -o umod.o umod.s extra=umod.o ;; arm64) cp umod-arm64.c umod.c clang -c -o umod.o umod.c extra=umod.o ;; esac # Prepare copy of libcrypto.a with only the checked functions renamed and exported.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Jan 26 22:52:27 UTC 2024 - 5.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64.rules
// In fact, UMOD will be translated into UREM instruction, and UREM is originally translated into // UDIV and MSUB instructions. But if there is already an identical UDIV instruction just before or // after UREM (case like quo, rem := z/y, z%y), then the second UDIV instruction becomes redundant. // The purpose of this rule is to have this extra UDIV instruction removed in CSE pass.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 113.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARM64Ops.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 58.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteARM64.go
v0.AddArg2(x, y) v.AddArg3(x, y, v0) return true } // match: (UMOD _ (MOVDconst [1])) // result: (MOVDconst [0]) for { if v_1.Op != OpARM64MOVDconst || auxIntToInt64(v_1.AuxInt) != 1 { break } v.reset(OpARM64MOVDconst) v.AuxInt = int64ToAuxInt(0) return true } // match: (UMOD x (MOVDconst [c])) // cond: isPowerOfTwo64(c) // result: (ANDconst [c-1] x)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 608.6K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
}, outputs: []outputInfo{ {0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 }, }, }, { name: "UMOD", argLen: 2, asm: arm64.AUREM, reg: regInfo{ inputs: []inputInfo{ {0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)