// STNP <St>, <St2>, [<Xn|SP>{, #<imm_2>}]
	{0xffc00000, 0x2c000000, STNP, instArgs{arg_St, arg_St2, arg_Xns_mem_optional_imm7_4_signed}, nil},
	// STNP <Dt>, <Dt2>, [<Xn|SP>{, #<imm>}]
	{0xffc00000, 0x6c000000, STNP, instArgs{arg_Dt, arg_Dt2, arg_Xns_mem_optional_imm7_8_signed}, nil},
	// STNP <Qt>, <Qt2>, [<Xn|SP>{, #<imm_1>}]

{"Name":"STNP (SIMD&FP)","Bits":"00:2|1|0|1|1|0|0|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"32-bit variant","Syntax":"STNP <St1>, <St2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},
{"Name":"STNP (SIMD&FP)","Bits":"01:2|1|0|1|1|0|0|0|0|imm7:7|Rt2:5|Rn:5|Rt:5","Arch":"64-bit variant","Syntax":"STNP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}]","Code":"","Alias":""},

	STLXP (R6, R3), (R10), R2                  // 468d22c8
	STLXPW (R6, R11), (R22), R21               // c6ae3588
	//TODO STNPW 44(R1), R3, R10               // 2a8c0528
	//TODO STNP 0x108(R3), ZR, R7              // 67fc10a8
	LDP.P -384(R3), (R22, R26)                 // 7668e8a8
	LDP.W 280(R8), (R19, R11)                  // 13add1a9
	STP.P (R22, R27), 352(R0)                  // 166c96a8