relocs := ldr.Relocs(s)
		for ri := 0; ri < relocs.Count(); ri++ {
			r := relocs.At(ri)
			if r.Type() != objabi.R_RISCV_CALL && r.Type() != objabi.R_RISCV_PCREL_ITYPE &&
				r.Type() != objabi.R_RISCV_PCREL_STYPE && r.Type() != objabi.R_RISCV_TLS_IE {
				continue
			}
			if r.Off() == 0 && ldr.SymType(s) == sym.STEXT {
				// Use the symbol for the function instead of creating
				// an overlapping symbol.

	_ = x[R_ADDRPOWER_TOCREL_DS-57]
	_ = x[R_ADDRPOWER_D34-58]
	_ = x[R_ADDRPOWER_PCREL34-59]
	_ = x[R_RISCV_JAL-60]
	_ = x[R_RISCV_JAL_TRAMP-61]
	_ = x[R_RISCV_CALL-62]
	_ = x[R_RISCV_PCREL_ITYPE-63]
	_ = x[R_RISCV_PCREL_STYPE-64]
	_ = x[R_RISCV_TLS_IE-65]
	_ = x[R_RISCV_TLS_LE-66]
	_ = x[R_RISCV_GOT_HI20-67]
	_ = x[R_RISCV_PCREL_HI20-68]
	_ = x[R_RISCV_PCREL_LO12_I-69]
	_ = x[R_RISCV_PCREL_LO12_S-70]
	_ = x[R_RISCV_BRANCH-71]

	R_RISCV_CALL

	// R_RISCV_PCREL_ITYPE resolves a 32 bit PC-relative address for an
	// AUIPC + I-type instruction pair.
	R_RISCV_PCREL_ITYPE

	// R_RISCV_PCREL_STYPE resolves a 32 bit PC-relative address for an
	// AUIPC + S-type instruction pair.
	R_RISCV_PCREL_STYPE

	// R_RISCV_TLS_IE resolves a 32 bit TLS initial-exec address for an
	// AUIPC + I-type instruction pair.
	R_RISCV_TLS_IE

	// R_RISCV_PCREL_ITYPE relocation.
	NEED_PCREL_ITYPE_RELOC

	// NEED_PCREL_STYPE_RELOC is set on AUIPC instructions to indicate that
	// it is the first instruction in an AUIPC + S-type pair that needs a
	// R_RISCV_PCREL_STYPE relocation.
	NEED_PCREL_STYPE_RELOC
)

// RISC-V mnemonics, as defined in the "opcodes" and "opcodes-pseudo" files
// at https://github.com/riscv/riscv-opcodes.
//

			} else if p.Mark&NEED_PCREL_ITYPE_RELOC == NEED_PCREL_ITYPE_RELOC {
				rt = objabi.R_RISCV_PCREL_ITYPE
				addr = &p.From
			} else if p.Mark&NEED_PCREL_STYPE_RELOC == NEED_PCREL_STYPE_RELOC {
				rt = objabi.R_RISCV_PCREL_STYPE
				addr = &p.To
			} else {
				break
			}
			if p.As == AAUIPC {
				if p.Link == nil {
					ctxt.Diag("AUIPC needing PC-relative reloc missing following instruction")
					break