(SUB (SRAconst [c] y) x) => (RSBshiftRA x y [c])
(SUB x (SLL y z)) => (SUBshiftLLreg x y z)
(SUB (SLL y z) x) => (RSBshiftLLreg x y z)
(SUB x (SRL y z)) => (SUBshiftRLreg x y z)
(SUB (SRL y z) x) => (RSBshiftRLreg x y z)
(SUB x (SRA y z)) => (SUBshiftRAreg x y z)
(SUB (SRA y z) x) => (RSBshiftRAreg x y z)
(SBC x (SLLconst [c] y) flags) => (SBCshiftLL x y [c] flags)
(SBC (SLLconst [c] y) x flags) => (RSCshiftLL x y [c] flags)

		{name: "SUBshiftRAreg", argLength: 3, reg: gp31, asm: "SUB"}, // arg0 - arg1>>arg2, signed shift
		{name: "RSBshiftLLreg", argLength: 3, reg: gp31, asm: "RSB"}, // arg1<<arg2 - arg0
		{name: "RSBshiftRLreg", argLength: 3, reg: gp31, asm: "RSB"}, // arg1>>arg2 - arg0, unsigned shift
		{name: "RSBshiftRAreg", argLength: 3, reg: gp31, asm: "RSB"}, // arg1>>arg2 - arg0, signed shift

			break
		}
		z := v_0.Args[1]
		y := v_0.Args[0]
		x := v_1
		v.reset(OpARMSUBshiftLLreg)
		v.AddArg3(x, y, z)
		return true
	}
	// match: (RSB x (SRL y z))
	// result: (RSBshiftRLreg x y z)
	for {
		x := v_0
		if v_1.Op != OpARMSRL {
			break
		}
		z := v_1.Args[1]
		y := v_1.Args[0]
		v.reset(OpARMRSBshiftRLreg)
		v.AddArg3(x, y, z)
		return true
	}

				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
			outputs: []outputInfo{
				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
			},
		},
	},
	{
		name:   "RSBshiftRLreg",
		argLen: 3,
		asm:    arm.ARSB,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14