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Results 1 - 4 of 4 for SUBshiftRAreg (0.19 sec)
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src/cmd/compile/internal/ssa/_gen/ARM.rules
(SUB x (SLL y z)) => (SUBshiftLLreg x y z) (SUB (SLL y z) x) => (RSBshiftLLreg x y z) (SUB x (SRL y z)) => (SUBshiftRLreg x y z) (SUB (SRL y z) x) => (RSBshiftRLreg x y z) (SUB x (SRA y z)) => (SUBshiftRAreg x y z) (SUB (SRA y z) x) => (RSBshiftRAreg x y z) (SBC x (SLLconst [c] y) flags) => (SBCshiftLL x y [c] flags) (SBC (SLLconst [c] y) x flags) => (RSCshiftLL x y [c] flags)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 90.1K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/_gen/ARMOps.go
{name: "SUBshiftLLreg", argLength: 3, reg: gp31, asm: "SUB"}, // arg0 - arg1<<arg2 {name: "SUBshiftRLreg", argLength: 3, reg: gp31, asm: "SUB"}, // arg0 - arg1>>arg2, unsigned shift {name: "SUBshiftRAreg", argLength: 3, reg: gp31, asm: "SUB"}, // arg0 - arg1>>arg2, signed shift {name: "RSBshiftLLreg", argLength: 3, reg: gp31, asm: "RSB"}, // arg1<<arg2 - arg0
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Feb 24 00:21:13 UTC 2023 - 41K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/rewriteARM.go
break } z := v_1.Args[1] y := v_1.Args[0] v.reset(OpARMRSBshiftRAreg) v.AddArg3(x, y, z) return true } // match: (RSB (SRA y z) x) // result: (SUBshiftRAreg x y z) for { if v_0.Op != OpARMSRA { break } z := v_0.Args[1] y := v_0.Args[0] x := v_1 v.reset(OpARMSUBshiftRAreg) v.AddArg3(x, y, z) return true }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 486.8K bytes - Viewed (0) -
src/cmd/compile/internal/ssa/opGen.go
{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, outputs: []outputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 }, }, }, { name: "SUBshiftRAreg", argLen: 3, asm: arm.ASUB, reg: regInfo{ inputs: []inputInfo{ {0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14 {1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu May 23 15:49:20 UTC 2024 - 1M bytes - Viewed (0)