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Results 1 - 4 of 4 for RORWconst (0.13 sec)

  1. src/cmd/compile/internal/ssa/_gen/ARM64Ops.go

    		{name: "RORconst", argLength: 1, reg: gp11, asm: "ROR", aux: "Int64"},     // arg0 right rotate by auxInt bits, auxInt should be in the range 0 to 63.
    		{name: "RORWconst", argLength: 1, reg: gp11, asm: "RORW", aux: "Int64"},   // uint32(arg0) right rotate by auxInt bits, auxInt should be in the range 0 to 31.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 58.8K bytes
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  2. src/cmd/compile/internal/ssa/_gen/ARM64.rules

    (CMPW x (MOVDconst [c])) => (CMPWconst [int32(c)] x)
    (CMPW (MOVDconst [c]) x) => (InvertFlags (CMPWconst [int32(c)] x))
    
    (ROR  x (MOVDconst [c])) => (RORconst x [c&63])
    (RORW x (MOVDconst [c])) => (RORWconst x [c&31])
    
    (ADDSflags x (MOVDconst [c]))  => (ADDSconstflags [c] x)
    
    (ADDconst [c] y) && c < 0 => (SUBconst [-c] y)
    
    // Canonicalize the order of arguments to comparisons - helps with CSE.
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 113.1K bytes
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  3. src/cmd/compile/internal/ssa/rewriteARM64.go

    		return true
    	}
    	return false
    }
    func rewriteValueARM64_OpARM64RORW(v *Value) bool {
    	v_1 := v.Args[1]
    	v_0 := v.Args[0]
    	// match: (RORW x (MOVDconst [c]))
    	// result: (RORWconst x [c&31])
    	for {
    		x := v_0
    		if v_1.Op != OpARM64MOVDconst {
    			break
    		}
    		c := auxIntToInt64(v_1.AuxInt)
    		v.reset(OpARM64RORWconst)
    		v.AuxInt = int64ToAuxInt(c & 31)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 608.6K bytes
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  4. src/cmd/compile/internal/ssa/opGen.go

    			},
    			outputs: []outputInfo{
    				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
    			},
    		},
    	},
    	{
    		name:    "RORWconst",
    		auxType: auxInt64,
    		argLen:  1,
    		asm:     arm64.ARORW,
    		reg: regInfo{
    			inputs: []inputInfo{
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 1M bytes
    - Viewed (0)
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