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Results 1 - 5 of 5 for REG_W0 (0.32 sec)

  1. src/cmd/internal/obj/mips/list0.go

    	}
    	if REG_M0 <= r && r <= REG_M31 {
    		return fmt.Sprintf("M%d", r-REG_M0)
    	}
    	if REG_FCR0 <= r && r <= REG_FCR31 {
    		return fmt.Sprintf("FCR%d", r-REG_FCR0)
    	}
    	if REG_W0 <= r && r <= REG_W31 {
    		return fmt.Sprintf("W%d", r-REG_W0)
    	}
    	if r == REG_HI {
    		return "HI"
    	}
    	if r == REG_LO {
    		return "LO"
    	}
    
    	return fmt.Sprintf("Rgok(%d)", r-obj.RBaseMIPS)
    }
    
    func DRconv(a int) string {
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 04 19:06:44 UTC 2020
    - 2.5K bytes
    - Viewed (0)
  2. src/cmd/internal/obj/mips/a.out.go

    		panic("REG_F0 is not a multiple of 32")
    	}
    	if REG_M0%32 != 0 {
    		panic("REG_M0 is not a multiple of 32")
    	}
    	if REG_FCR0%32 != 0 {
    		panic("REG_FCR0 is not a multiple of 32")
    	}
    	if REG_W0%32 != 0 {
    		panic("REG_W0 is not a multiple of 32")
    	}
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Aug 08 12:17:12 UTC 2023
    - 7.6K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/arch/mips.go

    		}
    	case "M":
    		if 0 <= n && n <= 31 {
    			return mips.REG_M0 + n, true
    		}
    	case "R":
    		if 0 <= n && n <= 31 {
    			return mips.REG_R0 + n, true
    		}
    	case "W":
    		if 0 <= n && n <= 31 {
    			return mips.REG_W0 + n, true
    		}
    	}
    	return 0, false
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Wed Mar 04 19:06:44 UTC 2020
    - 1.7K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/arch/arch.go

    	}
    	for i := mips.REG_M0; i <= mips.REG_M31; i++ {
    		register[obj.Rconv(i)] = int16(i)
    	}
    	for i := mips.REG_FCR0; i <= mips.REG_FCR31; i++ {
    		register[obj.Rconv(i)] = int16(i)
    	}
    	for i := mips.REG_W0; i <= mips.REG_W31; i++ {
    		register[obj.Rconv(i)] = int16(i)
    	}
    	register["HI"] = mips.REG_HI
    	register["LO"] = mips.REG_LO
    	// Pseudo-registers.
    	register["SB"] = RSB
    	register["FP"] = RFP
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 21 06:51:28 UTC 2023
    - 21.3K bytes
    - Viewed (0)
  5. src/cmd/internal/obj/mips/asm0.go

    		if REG_F0 <= a.Reg && a.Reg <= REG_F31 {
    			return C_FREG
    		}
    		if REG_M0 <= a.Reg && a.Reg <= REG_M31 {
    			return C_MREG
    		}
    		if REG_FCR0 <= a.Reg && a.Reg <= REG_FCR31 {
    			return C_FCREG
    		}
    		if REG_W0 <= a.Reg && a.Reg <= REG_W31 {
    			return C_WREG
    		}
    		if a.Reg == REG_LO {
    			return C_LO
    		}
    		if a.Reg == REG_HI {
    			return C_HI
    		}
    		return C_GOK
    
    	case obj.TYPE_MEM:
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Apr 16 17:46:09 UTC 2024
    - 53.6K bytes
    - Viewed (0)
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