// It doesn't cost much and is much more future-proof.
const CacheLinePadSize = 128

func doinit() {
	options = []option{
		{Name: "aes", Feature: &ARM64.HasAES},
		{Name: "pmull", Feature: &ARM64.HasPMULL},
		{Name: "sha1", Feature: &ARM64.HasSHA1},
		{Name: "sha2", Feature: &ARM64.HasSHA2},
		{Name: "sha512", Feature: &ARM64.HasSHA512},
		{Name: "crc32", Feature: &ARM64.HasCRC32},

	hwcap_EVTSTRM   = 1 << 21

	hwcap2_AES   = 1 << 0
	hwcap2_PMULL = 1 << 1
	hwcap2_SHA1  = 1 << 2
	hwcap2_SHA2  = 1 << 3
	hwcap2_CRC32 = 1 << 4
)

func initOptions() {
	options = []option{
		{Name: "pmull", Feature: &ARM.HasPMULL},
		{Name: "sha1", Feature: &ARM.HasSHA1},
		{Name: "sha2", Feature: &ARM.HasSHA2},
		{Name: "swp", Feature: &ARM.HasSWP},
		{Name: "thumb", Feature: &ARM.HasTHUMB},

		{Name: "aes", Feature: &ARM64.HasAES},
		{Name: "fphp", Feature: &ARM64.HasFPHP},
		{Name: "jscvt", Feature: &ARM64.HasJSCVT},
		{Name: "lrcpc", Feature: &ARM64.HasLRCPC},
		{Name: "pmull", Feature: &ARM64.HasPMULL},
		{Name: "sha1", Feature: &ARM64.HasSHA1},
		{Name: "sha2", Feature: &ARM64.HasSHA2},
		{Name: "sha3", Feature: &ARM64.HasSHA3},
		{Name: "sha512", Feature: &ARM64.HasSHA512},

	// Large Systems Extension
	LSE bool
	// ARM v8.0 Cryptographic Extension. It includes the following features:
	// * FEAT_AES, which includes the AESD and AESE instructions.
	// * FEAT_PMULL, which includes the PMULL, PMULL2 instructions.
	// * FEAT_SHA1, which includes the SHA1* instructions.
	// * FEAT_SHA256, which includes the SHA256* instructions.
	Crypto bool
}

func (g Goarm64Features) String() string {

	NEG:       "NEG",
	NEGS:      "NEGS",
	NGC:       "NGC",
	NGCS:      "NGCS",
	NOP:       "NOP",
	NOT:       "NOT",
	ORN:       "ORN",
	ORR:       "ORR",
	PMUL:      "PMUL",
	PMULL:     "PMULL",
	PMULL2:    "PMULL2",
	PRFM:      "PRFM",
	PRFUM:     "PRFUM",
	RADDHN:    "RADDHN",
	RADDHN2:   "RADDHN2",
	RBIT:      "RBIT",
	RET:       "RET",
	REV:       "REV",
	REV16:     "REV16",

{"Name":"PMULL, PMULL2","Bits":"0|0|0|0|1|1|1|0|size:2|1|Rm:5|1|1|1|0|0|0|Rn:5|Rd:5","Arch":"Three registers, not all the same type variant","Syntax":"PMULL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>","Code":"","Alias":""},