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Results 1 - 3 of 3 for OK (0.17 sec)
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src/cmd/asm/internal/asm/testdata/ppc64.s
// Hex constant 0xFFFFFFFE00010001 ADD $-8589869055, R5 // 3fe0fffe63ff00017bff83e463ff00017cbf2a14 or 0602000138a50001 //TODO: this compiles to add r5,r6,r0. It should be addi r5,r6,0. // this is OK since r0 == $0, but the latter is preferred. ADD $0, R6, R5 // 7ca60214 //TODO: the assembler rewrites these into ADDIS $19, R5, Rx and ADD $-10617, Rx, Rx, but the test only sees the first ADDIS
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Apr 24 15:53:25 GMT 2024 - 49K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64enc_extra.s
// EVEX: VCVTPD2DQ with Y suffix (VL=2). VCVTPD2DQY (BX), X20 // 62e1ff28e623 VCVTPD2DQY (R11), X30 // 6241ff28e633 // XED encoder uses EVEX.X=0 for these; most x86 tools use EVEX.X=1. // Either way is OK. VMOVQ SP, X20 // 62e1fd086ee4 or 62a1fd086ee4 VMOVQ BP, X20 // 62e1fd086ee5 or 62a1fd086ee5 VMOVQ R14, X20 // 62c1fd086ee6 or 6281fd086ee6 // "VMOVQ r/m64, xmm1"/6E vs "VMOVQ xmm2/m64, xmm1"/7E with mem operand.
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Apr 11 18:32:50 GMT 2023 - 57.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/amd64error.s
// .Z instructions VMOVDQA32.Z Z0, Z1 // ERROR "mask register must be specified for .Z instructions" VMOVDQA32.Z Z0, K0, Z1 // ERROR "invalid instruction" VMOVDQA32.Z Z0, K1, Z1 // ok RDPID (BX) // ERROR "invalid instruction"
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Jun 14 00:03:57 GMT 2023 - 8.9K bytes - Viewed (0)