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Results 1 - 10 of 12 for MRC (0.05 sec)
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platforms/software/dependency-management/src/main/java/org/gradle/api/internal/artifacts/DependencyManagementBuildTreeScopeServices.java
AbstractModuleMetadataCache persistentModuleMetadataCache = readOnlyCaches.map(mrc -> (AbstractModuleMetadataCache) new TwoStageModuleMetadataCache(timeProvider, mrc.moduleMetadataCache, writableCaches.moduleMetadataCache)).orElse(w...
Registered: Wed Jun 12 18:38:38 UTC 2024 - Last Modified: Mon May 27 12:34:44 UTC 2024 - 18.6K bytes - Viewed (0) -
src/cmd/asm/internal/arch/arm.go
return true } return false } // ARMMRCOffset implements the peculiar encoding of the MRC and MCR instructions. // The difference between MRC and MCR is represented by a bit high in the word, not // in the usual way by the opcode itself. Asm must use AMRC for both instructions, so // we return the opcode for MRC so that asm doesn't need to import obj/arm.
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Nov 18 17:59:44 UTC 2022 - 6.1K bytes - Viewed (0) -
src/runtime/tls_arm.s
// If the host does not support MRC the linker will replace it with // a call to runtime.read_tls_fallback which jumps to __kuser_get_tls. // The replacement function saves LR in R11 over the call to read_tls_fallback. // To make stack unwinding work, this function should NOT be marked as NOFRAME, // as it may contain a call, which clobbers LR even just temporarily. MRC 15, 0, R0, C13, C0, 3 // fetch TLS base pointer
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue May 10 20:38:07 UTC 2022 - 3.5K bytes - Viewed (0) -
src/runtime/sys_windows_arm.s
MOVW R5, R13 // free stack space MOVW R0, 12(R4) // save return value to libcall->r1 MOVW R1, 16(R4) // GetLastError MRC 15, 0, R1, C13, C0, 2 MOVW 0x34(R1), R0 MOVW R0, 20(R4) // store in libcall->err MOVM.IA.W (R13), [R4, R5, R15] TEXT runtime·getlasterror(SB),NOSPLIT,$0 MRC 15, 0, R0, C13, C0, 2 MOVW 0x34(R0), R0 MOVW R0, ret+0(FP) RET // Called by Windows as a Vectored Exception Handler (VEH).
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Thu Sep 21 15:56:43 UTC 2023 - 7.7K bytes - Viewed (0) -
src/cmd/internal/obj/arm/anames.go
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed Oct 16 15:58:33 UTC 2019 - 1.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/asm.go
x5 := p.getConstant(prog, op, &a[5]) // Cond is handled specially for this instruction. offset, MRC, ok := arch.ARMMRCOffset(op, cond, x0, x1, x2, x3, x4, x5) if !ok { p.errorf("unrecognized condition code .%q", cond) } prog.To.Offset = offset cond = "" prog.As = MRC // Both instructions are coded as MRC. break } if p.arch.Family == sys.PPC64 { prog.From = a[0]
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Wed May 22 02:04:54 UTC 2024 - 25.5K bytes - Viewed (0) -
src/cmd/internal/obj/arm/a.out.go
AREV16 AREVSH ARBIT AXTAB AXTAH AXTABU AXTAHU ABFX ABFXU ABFC ABFI AMULWT AMULWB AMULBB AMULAWT AMULAWB AMULABB AMRC // MRC/MCR ALAST // aliases AB = obj.AJMP ABL = obj.ACALL ) /* scond byte */ const ( C_SCOND = (1 << 4) - 1 C_SBIT = 1 << 4 C_PBIT = 1 << 5 C_WBIT = 1 << 6
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Apr 05 16:22:12 UTC 2021 - 7K bytes - Viewed (0) -
src/cmd/internal/obj/arm/obj5.go
} // Replace TLS register fetches on older ARM processors. switch p.As { // Treat MRC 15, 0, <reg>, C13, C0, 3 specially. case AMRC: if p.To.Offset&0xffff0fff == 0xee1d0f70 { // Because the instruction might be rewritten to a BL which returns in R0 // the register must be zero. if p.To.Offset&0xf000 != 0 { ctxt.Diag("%v: TLS MRC instruction must write to R0 as it might get translated into a BL instruction", p.Line()) }
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Mon Nov 20 17:19:36 UTC 2023 - 21.4K bytes - Viewed (0) -
src/runtime/sys_freebsd_arm.s
TEXT ·publicationBarrier(SB),NOSPLIT|NOFRAME,$0-0 B runtime·armPublicationBarrier(SB) // TODO(minux): this only supports ARMv6K+. TEXT runtime·read_tls_fallback(SB),NOSPLIT|NOFRAME,$0 WORD $0xee1d0f70 // mrc p15, 0, r0, c13, c0, 3 RET // func cpuset_getaffinity(level int, which int, id int64, size int, mask *byte) int32 TEXT runtime·cpuset_getaffinity(SB), NOSPLIT, $0-28 MOVW level+0(FP), R0 MOVW which+4(FP), R1
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Tue Jun 06 18:49:01 UTC 2023 - 10.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/arm.s
// (($11 & 15) << 0) | /* Crm */ // (($12 & 7) << 5) | /* coprocessor information */ // (1<<4)); /* must be set */ // outcode(AMRC, Always, &nullgen, 0, &g); // } MRC.S 4, 6, R1, C2, C3, 7 // MRC $8301712627 MCR.S 4, 6, R1, C2, C3, 7 // MRC $8300664051 // // MULL r1,r2,(hi,lo) // // LTYPEM cond reg ',' reg ',' regreg // { // outcode($1, $2, &$3, int32($5.Reg), &$7); // } MULL R1, R2, (R3,R4)
Registered: Wed Jun 12 16:32:35 UTC 2024 - Last Modified: Fri Dec 15 20:51:01 UTC 2023 - 69K bytes - Viewed (0)