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Results 1 - 5 of 5 for LDORALB (0.08 sec)

  1. src/cmd/internal/obj/arm64/anames.go

    	"LDEORALH",
    	"LDEORALW",
    	"LDEORAW",
    	"LDEORB",
    	"LDEORD",
    	"LDEORH",
    	"LDEORLB",
    	"LDEORLD",
    	"LDEORLH",
    	"LDEORLW",
    	"LDEORW",
    	"LDORAB",
    	"LDORAD",
    	"LDORAH",
    	"LDORALB",
    	"LDORALD",
    	"LDORALH",
    	"LDORALW",
    	"LDORAW",
    	"LDORB",
    	"LDORD",
    	"LDORH",
    	"LDORLB",
    	"LDORLD",
    	"LDORLH",
    	"LDORLW",
    	"LDORW",
    	"LDP",
    	"LDPSW",
    	"LDPW",
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 18 01:40:37 UTC 2023
    - 5.4K bytes
    - Viewed (0)
  2. src/internal/runtime/atomic/atomic_arm64.s

    #endif
    
    TEXT ·Or8(SB), NOSPLIT, $0-9
    	MOVD	ptr+0(FP), R0
    	MOVB	val+8(FP), R1
    #ifndef GOARM64_LSE
    	MOVBU	internal∕cpu·ARM64+const_offsetARM64HasATOMICS(SB), R4
    	CBZ 	R4, load_store_loop
    #endif
    	LDORALB	R1, (R0), R2
    	RET
    #ifndef GOARM64_LSE
    load_store_loop:
    	LDAXRB	(R0), R2
    	ORR	R1, R2
    	STLXRB	R2, (R0), R3
    	CBNZ	R3, load_store_loop
    	RET
    #endif
    
    // func And(addr *uint32, v uint32)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Mon Mar 25 19:53:03 UTC 2024
    - 9K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/arm64error.s

    	LDORALW	R5, (R6), RSP                                    // ERROR "illegal combination"
    	LDORALH	R5, (R6), RSP                                    // ERROR "illegal combination"
    	LDORALB	R5, (R6), RSP                                    // ERROR "illegal combination"
    	LDORD	R5, (R6), RSP                                    // ERROR "illegal combination"
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 08 03:28:17 UTC 2023
    - 37.8K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/arm64.s

    	LDORALW	R5, (RSP), R7                        // e733e5b8
    	LDORALH	R5, (R6), R7                         // c730e578
    	LDORALH	R5, (RSP), R7                        // e733e578
    	LDORALB	R5, (R6), R7                         // c730e538
    	LDORALB	R5, (RSP), R7                        // e733e538
    	LDORD	R5, (R6), R7                         // c73025f8
    	LDORD	R5, (RSP), R7                        // e73325f8
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Fri Dec 08 03:28:17 UTC 2023
    - 94.9K bytes
    - Viewed (0)
  5. src/cmd/compile/internal/ssa/_gen/ARM64Ops.go

    		// atomic and/or variant.
    		// *arg0 &= (|=) arg1. arg2=mem. returns <old content of *arg0, memory>. auxint must be zero.
    		//   AND:
    		// MNV       Rarg1, Rtemp
    		// LDANDALB  Rtemp, (Rarg0), Rout
    		//   OR:
    		// LDORALB  Rarg1, (Rarg0), Rout
    		{name: "LoweredAtomicAnd8Variant", argLength: 3, reg: gpxchg, resultNotInArgs: true, faultOnNilArg0: true, hasSideEffects: true, unsafePoint: true},
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Thu May 23 15:49:20 UTC 2024
    - 58.8K bytes
    - Viewed (0)
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