symname = func(uint64) (string, uint64) { return "", 0 }
	}

	var iargs []Arg
	for _, a := range inst.Args {
		if a == nil {
			break
		}
		iargs = append(iargs, a)
	}

	switch inst.Op {
	case INSB, INSD, INSW, OUTSB, OUTSD, OUTSW, LOOPNE, JCXZ, JECXZ, JRCXZ, LOOP, LOOPE, MOV, XLATB:
		if inst.Op == MOV && (inst.Opcode>>16)&0xFFFC != 0x0F20 {
			break
		}
		for i, p := range inst.Prefix {
			if p&0xFF == PrefixAddrSize {

	case Reg:
		switch inst.Op {
		case CVTSI2SS, CVTSI2SD, CVTSS2SI, CVTSD2SI, CVTTSD2SI, CVTTSS2SI:
			if inst.DataSize == 16 && EAX <= x && x <= R15L {
				x -= EAX - AX
			}

		case IN, INSB, INSW, INSD, OUT, OUTSB, OUTSW, OUTSD:
			// DX is the port, but libopcodes prints it as if it were a memory reference.
			if x == DX {
				return "(%dx)"
			}
		case VMOVDQA, VMOVDQU, VMOVNTDQA, VMOVNTDQ:

	"IDIVL",
	"IDIVQ",
	"IDIVW",
	"IMUL3L",
	"IMUL3Q",
	"IMUL3W",
	"IMULB",
	"IMULL",
	"IMULQ",
	"IMULW",
	"INB",
	"INCB",
	"INCL",
	"INCQ",
	"INCW",
	"INL",
	"INSB",
	"INSERTPS",
	"INSL",
	"INSW",
	"INT",
	"INTO",
	"INVD",
	"INVLPG",
	"INVPCID",
	"INW",
	"IRETL",
	"IRETQ",
	"IRETW",
	"JCC",
	"JCS",
	"JCXZL",
	"JCXZQ",

	// the best way to express the effect of the segment override prefixes.
	// TODO(rsc): Perhaps add these to the tables and
	// create bytecode instructions for them.
	usedAddrSize := false
	switch inst.Op {
	case INSB, INSW, INSD:
		inst.Args[0] = Mem{Segment: ES, Base: baseRegForBits(addrMode) + DI - AX}
		inst.Args[1] = DX
		usedAddrSize = true

	case OUTSB, OUTSW, OUTSD:
		inst.Args[0] = DX

	HSUBPD:          "HSUBPD",
	HSUBPS:          "HSUBPS",
	ICEBP:           "ICEBP",
	IDIV:            "IDIV",
	IMUL:            "IMUL",
	IN:              "IN",
	INC:             "INC",
	INSB:            "INSB",
	INSD:            "INSD",
	INSERTPS:        "INSERTPS",
	INSW:            "INSW",
	INT:             "INT",
	INTO:            "INTO",
	INVD:            "INVD",
	INVLPG:          "INVLPG",

	INCB (BX)                               // fe03
	INCB (R11)                              // 41fe03
	INCB DL                                 // fec2
	INCB R11                                // 41fec3
	INSB                                    // 6c
	INSL                                    // 6d
	INSERTPS $7, (BX), X2                   // 660f3a211307
	INSERTPS $7, (R11), X2                  // 66410f3a211307