// amd64:`MOVW\t\$12592, \(`,`MOVB\t\$50, 2\(`
	//   386:`MOVW\t\$12592, \(`,`MOVB\t\$50, 2\(`
	//   arm:`MOVW\t\$48`,`MOVW\t\$49`,`MOVW\t\$50`
	// arm64:`MOVD\t\$12592`,`MOVD\t\$50`
	//  wasm:`I64Const\t\$12592`,`I64Store16\t\$0`,`I64Const\t\$50`,`I64Store8\t\$2`
	// mips64:`MOVV\t\$48`,`MOVV\t\$49`,`MOVV\t\$50`
	bsink = []byte("012")

	// 858927408 = 0x33323130
	//     13620 = 0x3534
	// amd64:`MOVL\t\$858927408`,`MOVW\t\$13620, 4\(`

(Store {t} ptr val mem) && t.Size() == 4 => (I64Store32 ptr val mem)
(Store {t} ptr val mem) && t.Size() == 2 => (I64Store16 ptr val mem)
(Store {t} ptr val mem) && t.Size() == 1 => (I64Store8 ptr val mem)

// Lowering moves
(Move [0] _ _ mem) => mem
(Move [1] dst src mem) => (I64Store8 dst (I64Load8U src mem) mem)
(Move [2] dst src mem) => (I64Store16 dst (I64Load16U src mem) mem)
(Move [4] dst src mem) => (I64Store32 dst (I64Load32U src mem) mem)

	"I64Load8S",
	"I64Load8U",
	"I64Load16S",
	"I64Load16U",
	"I64Load32S",
	"I64Load32U",
	"I32Store",
	"I64Store",
	"F32Store",
	"F64Store",
	"I32Store8",
	"I32Store16",
	"I64Store8",
	"I64Store16",
	"I64Store32",
	"CurrentMemory",
	"GrowMemory",
	"I32Const",
	"I64Const",
	"F32Const",
	"F64Const",
	"I32Eqz",
	"I32Eq",
	"I32Ne",
	"I32LtS",
	"I32LtU",
	"I32GtS",
	"I32GtU",

		{name: "I64Store8", asm: "I64Store8", argLength: 3, reg: gpstore, aux: "Int64", typ: "Mem"},     // store 8-bit integer arg1 at address arg0+aux, arg2=mem, returns mem
		{name: "I64Store16", asm: "I64Store16", argLength: 3, reg: gpstore, aux: "Int64", typ: "Mem"},   // store 16-bit integer arg1 at address arg0+aux, arg2=mem, returns mem

	}
	return false
}
func rewriteValueWasm_OpWasmI64Store16(v *Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (I64Store16 [off] (I64AddConst [off2] ptr) val mem)
	// cond: isU32Bit(off+off2)
	// result: (I64Store16 [off+off2] ptr val mem)
	for {
		off := auxIntToInt64(v.AuxInt)
		if v_0.Op != OpWasmI64AddConst {
			break
		}
		off2 := auxIntToInt64(v_0.AuxInt)

				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
			},
		},
	},
	{
		name:    "I64Store16",
		auxType: auxInt64,
		argLen:  3,
		asm:     wasm.AI64Store16,
		reg: regInfo{
			inputs: []inputInfo{
				{1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP