(Move [5] dst src mem) =>
	(I64Store8 [4] dst (I64Load8U [4] src mem)
		(I64Store32 dst (I64Load32U src mem) mem))
(Move [6] dst src mem) =>
	(I64Store16 [4] dst (I64Load16U [4] src mem)
		(I64Store32 dst (I64Load32U src mem) mem))
(Move [7] dst src mem) =>
	(I64Store32 [3] dst (I64Load32U [3] src mem)
		(I64Store32 dst (I64Load32U src mem) mem))
(Move [s] dst src mem) && s > 8 && s < 16 =>

	"I32Load",
	"I64Load",
	"F32Load",
	"F64Load",
	"I32Load8S",
	"I32Load8U",
	"I32Load16S",
	"I32Load16U",
	"I64Load8S",
	"I64Load8U",
	"I64Load16S",
	"I64Load16U",
	"I64Load32S",
	"I64Load32U",
	"I32Store",
	"I64Store",
	"F32Store",
	"F64Store",
	"I32Store8",
	"I32Store16",
	"I64Store8",
	"I64Store16",
	"I64Store32",
	"CurrentMemory",
	"GrowMemory",
	"I32Const",
	"I64Const",

		{name: "I64Load16S", asm: "I64Load16S", argLength: 2, reg: gpload, aux: "Int64", typ: "Int16"},  // read signed 16-bit integer from address arg0+aux, arg1=mem
		{name: "I64Load32U", asm: "I64Load32U", argLength: 2, reg: gpload, aux: "Int64", typ: "UInt32"}, // read unsigned 32-bit integer from address arg0+aux, arg1=mem

	Get CTXT; \
	I32WrapI64; \
	I64Load $0; \
	CALL; \
	\
	I64Load32U stackRetOffset+28(FP); \
	Set R0; \
	\
	MOVD stackArgsType+0(FP), RET0; \
	\
	I64Load stackArgs+16(FP); \
	Get R0; \
	I64Add; \
	Set RET1; \
	\
	Get SP; \
	I64ExtendI32U; \
	Get R0; \
	I64Add; \
	Set RET2; \
	\
	I64Load32U stackArgsSize+24(FP); \
	Get R0; \
	I64Sub; \
	Set RET3; \
	\

		v2.AddArg2(src, mem)
		v1.AddArg3(dst, v2, mem)
		v.AddArg3(dst, v0, v1)
		return true
	}
	// match: (Move [7] dst src mem)
	// result: (I64Store32 [3] dst (I64Load32U [3] src mem) (I64Store32 dst (I64Load32U src mem) mem))
	for {
		if auxIntToInt64(v.AuxInt) != 7 {
			break
		}
		dst := v_0
		src := v_1
		mem := v_2
		v.reset(OpWasmI64Store32)
		v.AuxInt = int64ToAuxInt(3)

			},
			outputs: []outputInfo{
				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
			},
		},
	},
	{
		name:    "I64Load32U",
		auxType: auxInt64,
		argLen:  2,
		asm:     wasm.AI64Load32U,
		reg: regInfo{
			inputs: []inputInfo{
				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB