FYL2XP1                                 // d9f9
	HADDPD (BX), X2                         // 660f7c13
	HADDPD (R11), X2                        // 66410f7c13
	HADDPD X2, X2                           // 660f7cd2
	HADDPD X11, X2                          // 66410f7cd3
	HADDPD (BX), X11                        // 66440f7c1b
	HADDPD (R11), X11                       // 66450f7c1b
	HADDPD X2, X11                          // 66440f7cda

	VADDPD X30, X29, X10        // 6211950058d6
	VADDPD X12, X11, X28        // 6241a50858e4
	VADDPD X30, X11, X28        // 6201a50858e6
	VADDPD X12, X29, X28        // 6241950058e4
	VADDPD X30, X29, X28        // 6201950058e6
	VADDPD (AX), X29, X0        // 62f195005800
	VADDPD (AX), X1, X28        // 6261f5085820
	VADDPD (AX), X29, X28       // 626195005820
	VADDPD (AX), X29, X10       // 627195005810

//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	ABSD	F1, F2

//	LFADD freg ',' freg
//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	ADDD	F1, F2

//	LFADD freg ',' freg ',' freg
//	{
//		outcode(int($1), &$2, int($4.Reg), &$6);
//	}
	ADDD	F1, F2, F3

//	LFCMP freg ',' freg
//	{
//		outcode(int($1), &$2, 0, &$4);
//	}
	CMPEQD	F1, F2


//
// WORD
//

	FLD	(X5), F0				// 07b00200
	FLD	4(X5), F0				// 07b04200
	FSD	F0, (X5)				// 27b00200
	FSD	F0, 4(X5)				// 27b20200

	// 12.4: Double-Precision Floating-Point Computational Instructions
	FADDD	F1, F0, F2				// 53011002
	FSUBD	F1, F0, F2				// 5301100a
	FMULD	F1, F0, F2				// 53011012
	FDIVD	F1, F0, F2				// 5301101a
	FMIND	F1, F0, F2				// 5301102a
	FMAXD	F1, F0, F2				// 5311102a

	FMOVS	(F2), F0                                         // ERROR "illegal combination"
	FMOVD	F0, (F1)                                         // ERROR "illegal combination"
	LDADDAD	R5, (R6), RSP                                    // ERROR "illegal combination"
	LDADDAW	R5, (R6), RSP                                    // ERROR "illegal combination"

	// Usage of rounding with invalid operands.
	VADDPD.RU_SAE X3, X2, K1, X1     // ERROR "unsupported rounding"
	VADDPD.RD_SAE X3, X2, K1, X1     // ERROR "unsupported rounding"
	VADDPD.RZ_SAE X3, X2, K1, X1     // ERROR "unsupported rounding"
	VADDPD.RN_SAE X3, X2, K1, X1     // ERROR "unsupported rounding"
	VADDPD.RU_SAE Y3, Y2, K1, Y1     // ERROR "unsupported rounding"
	VADDPD.RD_SAE Y3, Y2, K1, Y1     // ERROR "unsupported rounding"

	VADDPD Z13, Z11, K3, Z14                           // 6251a54b58f5
	VADDPD Z14, Z11, K3, Z14                           // 6251a54b58f6
	VADDPD Z13, Z5, K3, Z14                            // 6251d54b58f5
	VADDPD Z14, Z5, K3, Z14                            // 6251d54b58f6
	VADDPD Z13, Z11, K3, Z27                           // 6241a54b58dd
	VADDPD Z14, Z11, K3, Z27                           // 6241a54b58de

// LTYPERT spec10	{ outcode($1, &$2); }
	JCS	2(PC)
	RETFL	$4

// Was bug: LOOP is a branch instruction.
	JCS	2(PC)
loop:
	LOOP	loop // LOOP

	// Intel pseudonyms for our own renamings.
	PADDD	M2, M1 // PADDL M2, M1
	MOVDQ2Q	X1, M1 // MOVQ X1, M1
	MOVNTDQ	X1, (AX)	// MOVNTO X1, (AX)
	MOVOA	(AX), X1	// MOVO (AX), X1

// Tests for SP indexed addresses.
	MOVQ	foo(SP)(AX*1), BX		// 488b1c04

// license that can be found in the LICENSE file.

#include "../../../../../runtime/textflag.h"

TEXT	foo(SB), DUPOK|NOSPLIT, $0

	ADDF	F0, F1, F2    // 002a31ee
	ADDD.EQ	F3, F4, F5    // 035b340e
	ADDF.NE	F0, F2        // 002a321e
	ADDD	F3, F5        // 035b35ee
	SUBF	F0, F1, F2    // 402a31ee
	SUBD.EQ	F3, F4, F5    // 435b340e
	SUBF.NE	F0, F2        // 402a321e
	SUBD	F3, F5        // 435b35ee

TEXT asmtest_avx512bw(SB), NOSPLIT, $0
	KADDD K4, K7, K5                                   // c4e1c54aec
	KADDD K6, K7, K5                                   // c4e1c54aee
	KADDD K4, K6, K5                                   // c4e1cd4aec
	KADDD K6, K6, K5                                   // c4e1cd4aee
	KADDD K4, K7, K4                                   // c4e1c54ae4
	KADDD K6, K7, K4                                   // c4e1c54ae6