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src/cmd/asm/internal/asm/testdata/mips64.s
BEQ R1, R2, label2 // BEQ R1, R2, 20 // 1022fffd // // other integer conditional branch // // LBRA rreg ',' rel // { // outcode(int($1), &$2, 0, &$4); // } label3: BLTZ R1, 1(PC) // BLTZ R1, 1(PC) // 04200001 BLTZ R1, label3 // BLTZ R1, 22 // 0420fffd // // floating point conditional branch // // LBRA rel label4: BFPT 1(PC) // BFPT 1(PC) // 4501000100000000
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Tue Aug 08 12:17:12 GMT 2023 - 12.4K bytes - Viewed (0) -
src/cmd/asm/internal/asm/parse.go
} switch reg { case "FP": addr.Name = obj.NAME_PARAM case "PC": if prefix != 0 { p.errorf("illegal addressing mode for PC") } addr.Type = obj.TYPE_BRANCH // We set the type and leave NAME untouched. See asmJump. case "SB": addr.Name = obj.NAME_EXTERN if isStatic { addr.Name = obj.NAME_STATIC } case "SP":
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Feb 21 14:34:57 GMT 2024 - 36.9K bytes - Viewed (0) -
api/go1.10.txt
pkg debug/macho, const ARM_RELOC_SECTDIFF RelocTypeARM pkg debug/macho, const ARM_RELOC_VANILLA = 0 pkg debug/macho, const ARM_RELOC_VANILLA RelocTypeARM pkg debug/macho, const ARM_THUMB_32BIT_BRANCH = 7 pkg debug/macho, const ARM_THUMB_32BIT_BRANCH RelocTypeARM pkg debug/macho, const ARM_THUMB_RELOC_BR22 = 6 pkg debug/macho, const ARM_THUMB_RELOC_BR22 RelocTypeARM pkg debug/macho, const FlagAllModsBound = 4096
Plain Text - Registered: Tue May 07 11:14:38 GMT 2024 - Last Modified: Tue Feb 06 05:00:01 GMT 2018 - 30.1K bytes - Viewed (0) -
src/cmd/asm/internal/asm/asm.go
if targetProg == nil { p.errorf("undefined label %s", patch.label) return } p.branch(patch.addr, targetProg) } p.toPatch = p.toPatch[:0] } func (p *Parser) branch(addr *obj.Addr, target *obj.Prog) { *addr = obj.Addr{ Type: obj.TYPE_BRANCH, Index: 0, } addr.Val = target } // asmInstruction assembles an instruction. // MOVW R9, (R10)
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Wed Feb 21 14:34:57 GMT 2024 - 25.3K bytes - Viewed (0) -
api/go1.11.txt
pkg debug/elf, const R_RISCV_ADD8 = 33 pkg debug/elf, const R_RISCV_ADD8 R_RISCV pkg debug/elf, const R_RISCV_ALIGN = 43 pkg debug/elf, const R_RISCV_ALIGN R_RISCV pkg debug/elf, const R_RISCV_BRANCH = 16 pkg debug/elf, const R_RISCV_BRANCH R_RISCV pkg debug/elf, const R_RISCV_CALL = 18 pkg debug/elf, const R_RISCV_CALL R_RISCV pkg debug/elf, const R_RISCV_CALL_PLT = 19 pkg debug/elf, const R_RISCV_CALL_PLT R_RISCV
Plain Text - Registered: Tue May 07 11:14:38 GMT 2024 - Last Modified: Wed Aug 22 03:48:56 GMT 2018 - 25K bytes - Viewed (2) -
src/cmd/asm/internal/asm/endtoend_test.go
i++ } continue } buf = append(buf, c) } f := strings.Fields(string(buf)) // Turn relative (PC) into absolute (PC) automatically, // so that most branch instructions don't need comments // giving the absolute form. if len(f) > 0 && strings.Contains(printed, "(PC)") { index := len(f) - 1 suf := "(PC)" for !strings.HasSuffix(f[index], suf) { index--
Go - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Thu Dec 07 18:42:59 GMT 2023 - 11.6K bytes - Viewed (0) -
src/cmd/asm/internal/asm/testdata/riscv64.s
// the real address and updates the immediate, using a trampoline in // the case where the address is not directly reachable. CALL asmtest(SB) // ef000000 JMP asmtest(SB) // 6f000000 // Branch pseudo-instructions BEQZ X5, 2(PC) // 63840200 BGEZ X5, 2(PC) // 63d40200 BGT X5, X6, 2(PC) // 63445300 BGTU X5, X6, 2(PC) // 63645300 BGTZ X5, 2(PC) // 63445000 BLE X5, X6, 2(PC) // 63545300
Others - Registered: Tue Apr 30 11:13:12 GMT 2024 - Last Modified: Fri Mar 22 04:42:21 GMT 2024 - 16.7K bytes - Viewed (1)