}
				prog.Reg = reg
			}
			break
		}
		if p.arch.Family == sys.MIPS || p.arch.Family == sys.MIPS64 || p.arch.Family == sys.RISCV64 {
			// 3-operand jumps.
			// First two must be registers
			target = &a[2]
			prog.From = a[0]
			prog.Reg = p.getRegister(prog, op, &a[1])
			break
		}
		if p.arch.Family == sys.Loong64 {
			// 3-operand jumps.
			// First two must be registers

                </mxCell>

                </mxCell>

                </mxCell>

                </mxCell>

                </mxCell>

                </mxCell>

                </mxCell>

                        .arch(settingsOs.getArch())
                        .family(settingsOs.getFamily())
                        .name(settingsOs.getName())
                        .version(settingsOs.getVersion())
                        .location("arch", toLocation(settingsOs.getLocation("arch")))
                        .location("family", toLocation(settingsOs.getLocation("family")))

			}
			a.Index = r1
			if scale != 0 && scale != 1 && (p.arch.Family == sys.ARM64 ||
				p.arch.Family == sys.PPC64) {
				// Support (R1)(R2) (no scaling) and (R1)(R2*1).
				p.errorf("%s doesn't support scaled register format", p.arch.Name)
			} else {
				a.Scale = int16(scale)
			}
		}
		p.get(')')
	} else if scale != 0 {
		if p.arch.Family == sys.ARM64 {