{0xfffffc00, 0x9e660000, FMOV, instArgs{arg_Xd, arg_Dn}, nil},
	// FMOV <Xd>, <Vn>.D[1]
	{0xfffffc00, 0x9eae0000, FMOV, instArgs{arg_Xd, arg_Vn_arrangement_D_index__1}, nil},
	// FMOV <Sd>, <Sn>
	{0xfffffc00, 0x1e204000, FMOV, instArgs{arg_Sd, arg_Sn}, nil},
	// FMOV <Dd>, <Dn>
	{0xfffffc00, 0x1e604000, FMOV, instArgs{arg_Dd, arg_Dn}, nil},
	// FMOV <Sd>, #<imm>

        (MOV(H|W|D)load [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
(FMOV(S|D)load [off1] {sym1} p:(MOVDaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2)
	&& ((is16Bit(int64(off1+off2)) && (ptr.Op != OpSB || p.Uses == 1)) || (supportsPPC64PCRel() && is32Bit(int64(off1+off2)))) =>
        (FMOV(S|D)load [off1+off2] {mergeSym(sym1,sym2)} ptr mem)

// Fold offsets for loads.

{"Name":"FMOV (register)","Bits":"0|0|0|1|1|1|1|0|01:2|1|0|0|0|0|0|0|1|0|0|0|0|Rn:5|Rd:5","Arch":"Double-precision variant","Syntax":"FMOV <Dd>, <Dn>","Code":"","Alias":""},
{"Name":"FMOV (general)","Bits":"0|0|0|1|1|1|1|0|00:2|1|00:2|111:3|0|0|0|0|0|0|Rn:5|Rd:5","Arch":"32-bit to single-precision variant","Syntax":"FMOV <Sd>, <Wn>","Code":"","Alias":""},

	CRnEQ represents CR bit 2 of CR field n. (0-7)
	CRnSO represents CR bit 3 of CR field n. (0-7)

# GOPPC64 >= power10 and its effects on Go asm

When GOPPC64=power10 is used to compile a Go program for ppc64le/linux, MOV*, FMOV*, and ADD
opcodes which would require 2 or more machine instructions to emulate a 32 bit constant, or
symbolic reference are implemented using prefixed instructions.

					} else if rno >= uint16(D0) && rno <= uint16(D31) {
						op = fmt.Sprintf("%sD", op)
					} else if rno <= uint16(WZR) {
						op += "W"
					}
				}
			}
		}

	case FMOV:
		for i := 0; i <= 1; i++ {
			if r, ok := inst.Args[i].(Reg); ok {
				rno := uint16(r)
				if rno >= uint16(S0) && rno <= uint16(S31) {
					op = fmt.Sprintf("%sS", op)
					break

(Select0 (F(ADDS|SUBS) (FMULS y z) x)) && x.Block.Func.useFMA(v) => (FM(ADDS|SUBS) x y z)

// Convert floating point comparisons against zero into 'load and test' instructions.
(F(CMP|CMPS) x (FMOV(D|S)const [0.0])) => (LT(D|E)BR x)
(F(CMP|CMPS) (FMOV(D|S)const [0.0]) x) => (InvertFlags (LT(D|E)BR <v.Type> x))

// FSUB, FSUBS, FADD, FADDS now produce a condition code representing the

		o1 = 0x18<<20 | 0xf90
		o1 |= (uint32(p.From.Reg) & 15) << 16
		o1 |= (uint32(p.Reg) & 15) << 0
		o1 |= (uint32(p.To.Reg) & 15) << 12
		o1 |= ((uint32(p.Scond) & C_SCOND) ^ C_SCOND_XOR) << 28

	case 80: /* fmov zfcon,freg */
		if p.As == AMOVD {
			o1 = 0xeeb00b00 // VMOV imm 64
			o2 = c.oprrr(p, ASUBD, int(p.Scond))
		} else {
			o1 = 0x0eb00a00 // VMOV imm 32
			o2 = c.oprrr(p, ASUBF, int(p.Scond))
		}

		if (p.As == AFMOVD || p.As == AFMOVS) && (fc == C_REG || fc == C_ZREG || tc == C_REG || tc == C_ZREG) {
			// FMOV Rx, Fy or FMOV Fy, Rx
			o1 = FPCVTI(0, 0, 0, 0, 6)
			if p.As == AFMOVD {
				o1 |= 1<<31 | 1<<22 // 64-bit
			}
			if fc == C_REG || fc == C_ZREG {
				o1 |= 1 << 16 // FMOV Rx, Fy
			}
		} else {
			o1 = c.oprrr(p, p.As)
		}
		o1 |= uint32(p.From.Reg&31)<<5 | uint32(p.To.Reg&31)

// constants
(Const(64|32|16|8) [val]) => (MOVDconst [int64(val)])
(Const(32|64)F    [val]) => (FMOV(S|D)const [float64(val)])
(ConstNil) => (MOVDconst [0])
(ConstBool [t]) => (MOVDconst [b2i(t)])

(Slicemask <t> x) => (SRAconst (NEG <t> x) [63])

// truncations

	case 62: // equivalent of Mul64 in math/bits
		zRRE(op_MLGR, uint32(p.To.Reg), uint32(p.From.Reg), asm)

	case 66:
		zRR(op_BCR, uint32(Never), 0, asm)

	case 67: // fmov $0 freg
		var opcode uint32
		switch p.As {
		case AFMOVS:
			opcode = op_LZER
		case AFMOVD:
			opcode = op_LZDR
		}
		zRRE(opcode, uint32(p.To.Reg), 0, asm)

	case 68: // movw areg reg