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Results 1 - 2 of 2 for FA1 (0.12 sec)

  1. test/fixedbugs/issue22881.go

    			fmt.Printf("RHS didn't panic, case f%d\n", i)
    		}()
    		if len(m) != 0 {
    			fmt.Printf("map insert happened, case f%d\n", i)
    		}
    	}
    
    	// Append slice.
    	for i, f := range []func(map[int][]int){
    		fa0, fa1, fa2, fa3,
    	} {
    		m := map[int][]int{}
    		func() { // wrapper to scope the defer.
    			defer func() {
    				recover()
    			}()
    			f(m) // Will panic. Shouldn't modify m.
    			fmt.Printf("RHS didn't panic, case fa%d\n", i)
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 20 01:47:07 UTC 2018
    - 2K bytes
    - Viewed (0)
  2. src/cmd/asm/internal/arch/arch.go

    	register["FT5"] = riscv.REG_FT5
    	register["FT6"] = riscv.REG_FT6
    	register["FT7"] = riscv.REG_FT7
    	register["FS0"] = riscv.REG_FS0
    	register["FS1"] = riscv.REG_FS1
    	register["FA0"] = riscv.REG_FA0
    	register["FA1"] = riscv.REG_FA1
    	register["FA2"] = riscv.REG_FA2
    	register["FA3"] = riscv.REG_FA3
    	register["FA4"] = riscv.REG_FA4
    	register["FA5"] = riscv.REG_FA5
    	register["FA6"] = riscv.REG_FA6
    	register["FA7"] = riscv.REG_FA7
    Registered: Wed Jun 12 16:32:35 UTC 2024
    - Last Modified: Tue Mar 21 06:51:28 UTC 2023
    - 21.3K bytes
    - Viewed (0)
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