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  1. src/cmd/asm/internal/asm/testdata/ppc64.s

    	FMOVDU (R3), F1                 // cc230000
    	FMOVS 4(R3), F1                 // c0230004
    	FMOVS (R3)(R4), F1              // 7c241c2e
    	FMOVS (R3)(R0), F1              // 7c201c2e
    	FMOVS (R3), F1                  // c0230000
    	FMOVSU 4(R3), F1                // c4230004
    	FMOVSU (R3)(R4), F1             // 7c241c6e
    	FMOVSU (R3)(R0), F1             // 7c201c6e
    	FMOVSU (R3), F1                 // c4230000
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Wed Apr 24 15:53:25 GMT 2024
    - 49K bytes
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  2. src/cmd/asm/internal/asm/testdata/armerror.s

    	FMULAD	F0, F1             // ERROR "illegal combination"
    	FMULAF	F0, F1             // ERROR "illegal combination"
    	FMULSD	F0, F1             // ERROR "illegal combination"
    	FMULSF	F0, F1             // ERROR "illegal combination"
    	FNMULAD	F0, F1             // ERROR "illegal combination"
    	FNMULAF	F0, F1             // ERROR "illegal combination"
    	FNMULSD	F0, F1             // ERROR "illegal combination"
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Nov 03 14:06:21 GMT 2017
    - 14.4K bytes
    - Viewed (0)
  3. src/cmd/asm/internal/asm/testdata/riscv64.s

    	FCVTDLU X5, F0					// 538032d2
    	FCVTSD	F0, F1					// d3001040
    	FCVTDS	F0, F1					// d3000042
    	FSGNJD	F1, F0, F2				// 53011022
    	FSGNJND	F1, F0, F2				// 53111022
    	FSGNJXD	F1, F0, F2				// 53211022
    	FMVXD	F0, X5					// d30200e2
    	FMVDX	X5, F0					// 538002f2
    	FMADDD	F1, F2, F3, F4				// 4382201a
    	FMSUBD	F1, F2, F3, F4				// 4782201a
    	FNMSUBD	F1, F2, F3, F4				// 4b82201a
    	FNMADDD	F1, F2, F3, F4				// 4f82201a
    
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Mar 22 04:42:21 GMT 2024
    - 16.7K bytes
    - Viewed (0)
  4. src/cmd/asm/internal/asm/testdata/mips.s

    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	ABSD	F1, F2
    
    	//	LFADD freg ',' freg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	ADDD	F1, F2
    
    	//	LFADD freg ',' freg ',' freg
    	//	{
    	//		outcode(int($1), &$2, int($4.Reg), &$6);
    	//	}
    	ADDD	F1, F2, F3
    
    	//	LFCMP freg ',' freg
    	//	{
    	//		outcode(int($1), &$2, 0, &$4);
    	//	}
    	CMPEQD	F1, F2
    
    
    	//
    	// WORD
    	//
    	WORD	$1
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Aug 08 12:17:12 GMT 2023
    - 6.7K bytes
    - Viewed (0)
  5. src/cmd/asm/internal/asm/testdata/armv6.s

    	FNMULSD F5, F6, F7    // 057b96ee
    	DIVF	F0, F1, F2    // 002a81ee
    	DIVD.EQ	F3, F4, F5    // 035b840e
    	DIVF.NE	F0, F2        // 002a821e
    	DIVD	F3, F5        // 035b85ee
    	NEGF	F0, F1        // 401ab1ee
    	NEGD	F4, F5        // 445bb1ee
    	ABSF	F0, F1        // c01ab0ee
    	ABSD	F4, F5        // c45bb0ee
    	SQRTF	F0, F1        // c01ab1ee
    	SQRTD	F4, F5        // c45bb1ee
    	MOVFD	F0, F1        // c01ab7ee
    	MOVDF	F4, F5        // c45bb7ee
    
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Thu Dec 21 16:30:51 GMT 2017
    - 4.6K bytes
    - Viewed (0)
  6. src/cmd/asm/internal/asm/testdata/arm64.s

    	FLDPD	11(RSP), (F1, F2)   // fb2f0091610b406d
    	FLDPD	1024(RSP), (F1, F2) // fb031091610b406d
    	FLDPD.W	8(RSP), (F1, F2)    // e18bc06d
    	FLDPD.P	8(RSP), (F1, F2)    // e18bc06c
    	FLDPD	-31(R0), (F1, F2)   // 1b7c00d1610b406d
    	FLDPD	-4(R0), (F1, F2)    // 1b1000d1610b406d
    	FLDPD	-8(R0), (F1, F2)    // 01887f6d
    	FLDPD	x(SB), (F1, F2)
    	FLDPD	x+8(SB), (F1, F2)
    	FLDPS	-5(R0), (F1, F2)    // 1b1400d1610b402d
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Fri Dec 08 03:28:17 GMT 2023
    - 94.9K bytes
    - Viewed (0)
  7. src/cmd/asm/internal/asm/testdata/riscv64error.s

    	SD	X5, 4294967296(X6)		// ERROR "constant 4294967296 too large"
    	SRLI	$1, X5, F1			// ERROR "expected integer register in rd position but got non-integer register F1"
    	SRLI	$1, F1, X5			// ERROR "expected integer register in rs1 position but got non-integer register F1"
    	FNES	F1, (X5)			// ERROR "needs an integer register output"
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Sun Apr 07 03:32:27 GMT 2024
    - 2.8K bytes
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  8. src/cmd/asm/internal/asm/testdata/ppc64_p10.s

    	PNOP                                    // 0700000000000000
    	PSTB R1, $1, 12345678(R2)               // 061000bc9822614e
    	PSTD R1, $1, 12345678(R2)               // 041000bcf422614e
    	PSTFD F1, $1, 12345678(R2)              // 061000bcd822614e
    	PSTFS F1, $1, 123456789(R7)             // 0610075bd027cd15
    	PSTH R1, $1, 12345678(R2)               // 061000bcb022614e
    	PSTQ R2, $1, 12345678(R2)               // 041000bcf042614e
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Thu Mar 23 20:52:57 GMT 2023
    - 14.3K bytes
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  9. src/cmd/asm/internal/asm/testdata/s390x.s

    	FIEBR	$0, F0, F1             // b3570010
    	FIDBR	$7, F2, F3             // b35f7032
    	FMADD	F1, F1, F1             // b31e1011
    	FMADDS	F1, F2, F3             // b30e3012
    	FMSUB	F4, F5, F5             // b31f5045
    	FMSUBS	F6, F6, F7             // b30f7066
    	LPDFR	F1, F2                 // b3700021
    	LNDFR	F3, F4                 // b3710043
    	CPSDR	F5, F6, F7             // b3725076
    	LTEBR	F1, F2                 // b3020021
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Wed Nov 22 03:55:32 GMT 2023
    - 21.6K bytes
    - Viewed (0)
  10. src/cmd/asm/internal/asm/testdata/mips64.s

    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	ABSD	F1, F2
    
    //	LFADD freg ',' freg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	ADDD	F1, F2
    
    //	LFADD freg ',' freg ',' freg
    //	{
    //		outcode(int($1), &$2, int($4.Reg), &$6);
    //	}
    	ADDD	F1, F2, F3
    
    //	LFCMP freg ',' freg
    //	{
    //		outcode(int($1), &$2, 0, &$4);
    //	}
    	CMPEQD	F1, F2
    
    
    //
    // WORD
    //
    Others
    - Registered: Tue Apr 30 11:13:12 GMT 2024
    - Last Modified: Tue Aug 08 12:17:12 GMT 2023
    - 12.4K bytes
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