// Signed divide by a negative constant.  Rewrite to divide by a positive constant.
(Div8  <t> n (Const8  [c])) && c < 0 && c != -1<<7  => (Neg8  (Div8  <t> n (Const8  <t> [-c])))
(Div16 <t> n (Const16 [c])) && c < 0 && c != -1<<15 => (Neg16 (Div16 <t> n (Const16 <t> [-c])))
(Div32 <t> n (Const32 [c])) && c < 0 && c != -1<<31 => (Neg32 (Div32 <t> n (Const32 <t> [-c])))

(Sub(64|32)F ...) => (F(64|32)Sub ...)

(Mul(64|32|16|8) ...) => (I64Mul ...)
(Mul(64|32)F ...) => (F(64|32)Mul ...)

(Div64 [false] x y) => (I64DivS x y)
(Div32 [false] x y) => (I64DivS (SignExt32to64 x) (SignExt32to64 y))
(Div16 [false] x y) => (I64DivS (SignExt16to64 x) (SignExt16to64 y))
(Div8          x y) => (I64DivS (SignExt8to64 x) (SignExt8to64 y))
(Div64u ...) => (I64DivU ...)
(Div32u x y) => (I64DivU (ZeroExt32to64 x) (ZeroExt32to64 y))

	{name: "Avg64u", argLength: 2, typ: "UInt64"}, // 64-bit platforms only

	// For Div16, Div32 and Div64, AuxInt non-zero means that the divisor has been proved to be not -1
	// or that the dividend is not the most negative value.
	{name: "Div8", argLength: 2},  // arg0 / arg1, signed
	{name: "Div8u", argLength: 2}, // arg0 / arg1, unsigned
	{name: "Div16", argLength: 2, aux: "Bool"},
	{name: "Div16u", argLength: 2},

(Div64 x y) => (DIVV x y)
(Div64u ...) => (DIVVU ...)
(Div32 x y) => (DIVV (SignExt32to64 x) (SignExt32to64 y))
(Div32u x y) => (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y))
(Div16 x y) => (DIVV (SignExt16to64 x) (SignExt16to64 y))
(Div16u x y) => (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y))
(Div8 x y) => (DIVV (SignExt8to64 x) (SignExt8to64 y))
(Div8u x y) => (DIVVU (ZeroExt8to64 x) (ZeroExt8to64 y))

(Mul(64|32)F ...) => (FMUL(D|S) ...)

(Div(64|32)F ...) => (FDIV(D|S) ...)

(Div64 x y [false])  => (DIV x y)
(Div64u ...) => (DIVU ...)
(Div32 x y [false])  => (DIVW x y)
(Div32u ...) => (DIVUW ...)
(Div16 x y [false])  => (DIVW  (SignExt16to32 x) (SignExt16to32 y))
(Div16u x y) => (DIVUW (ZeroExt16to32 x) (ZeroExt16to32 y))
(Div8 x y)   => (DIVW  (SignExt8to32 x)  (SignExt8to32 y))

(Mul(32|16|8) ...) => (MUL ...)
(Mul(32|64)F ...) => (MUL(F|D) ...)

(Hmul(32|32u) x y) => (Select0 (MUL(T|TU) x y))
(Mul32uhilo ...) => (MULTU ...)

(Div32 x y) => (Select1 (DIV x y))
(Div32u x y) => (Select1 (DIVU x y))
(Div16 x y) => (Select1 (DIV (SignExt16to32 x) (SignExt16to32 y)))
(Div16u x y) => (Select1 (DIVU (ZeroExt16to32 x) (ZeroExt16to32 y)))
(Div8 x y) => (Select1 (DIV (SignExt8to32 x) (SignExt8to32 y)))

(Div64 x y) => (Select1 (DIVV x y))
(Div64u x y) => (Select1 (DIVVU x y))
(Div32 x y) => (Select1 (DIVV (SignExt32to64 x) (SignExt32to64 y)))
(Div32u x y) => (Select1 (DIVVU (ZeroExt32to64 x) (ZeroExt32to64 y)))
(Div16 x y) => (Select1 (DIVV (SignExt16to64 x) (SignExt16to64 y)))
(Div16u x y) => (Select1 (DIVVU (ZeroExt16to64 x) (ZeroExt16to64 y)))
(Div8 x y) => (Select1 (DIVV (SignExt8to64 x) (SignExt8to64 y)))

(Select0 (Mul64uhilo x y)) => (MULHDU x y)
(Select1 (Mul64uhilo x y)) => (MULLD x y)

(Div64 [false] x y) => (DIVD x y)
(Div64u ...) => (DIVDU ...)
(Div32 [false] x y) => (DIVW x y)
(Div32u ...) => (DIVWU ...)
(Div16 [false]  x y) => (DIVW  (SignExt16to32 x) (SignExt16to32 y))
(Div16u x y) => (DIVWU (ZeroExt16to32 x) (ZeroExt16to32 y))
(Div8 x y) => (DIVW  (SignExt8to32 x) (SignExt8to32 y))
(Div8u x y) => (DIVWU (ZeroExt8to32 x) (ZeroExt8to32 y))

(Div64u ...) => (DIVDU ...)
// DIVW/DIVWU has a 64-bit dividend and a 32-bit divisor,
// so a sign/zero extension of the dividend is required.
(Div32  x y) => (DIVW  (MOVWreg x) y)
(Div32u x y) => (DIVWU (MOVWZreg x) y)
(Div16  x y) => (DIVW  (MOVHreg x) (MOVHreg y))
(Div16u x y) => (DIVWU (MOVHZreg x) (MOVHZreg y))
(Div8   x y) => (DIVW  (MOVBreg x) (MOVBreg y))
(Div8u  x y) => (DIVWU (MOVBZreg x) (MOVBZreg y))

(Hmul32u x y) => (SRAconst (UMULL <typ.UInt64> x y) [32])
(Select0 (Mul64uhilo x y)) => (UMULH x y)
(Select1 (Mul64uhilo x y)) => (MUL x y)

(Div64 [false] x y) => (DIV  x y)
(Div32 [false] x y) => (DIVW x y)
(Div16 [false] x y) => (DIVW (SignExt16to32 x) (SignExt16to32 y))
(Div16u x y) => (UDIVW (ZeroExt16to32 x) (ZeroExt16to32 y))
(Div8   x y) => (DIVW  (SignExt8to32  x) (SignExt8to32  y))