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// This input was created by taking the instruction productions in
// the old assembler's (8a's) grammar and hand-writing complete
// instructions for each rule, to guarantee we cover the same space.

#include "../../../../../runtime/textflag.h"

TEXT foo(SB), DUPOK|NOSPLIT, $0

// LTYPE1 nonrem	{ outcode(int($1), &$2); }
	SETCC	AX
	SETCC	foo+4(SB)

// LTYPE2 rimnon	{ outcode(int($1), &$2); }
	DIVB	AX
	DIVB	foo+4(SB)
	PUSHL	$foo+4(SB)

	// NOT pseudo-instruction
	NOT	X5					// 93c2f2ff
	NOT	X5, X6					// 13c3f2ff

	// NEG/NEGW pseudo-instructions
	NEG	X5					// b3025040
	NEG	X5, X6					// 33035040
	NEGW	X5					// bb025040
	NEGW	X5, X6					// 3b035040

	// This jumps to the second instruction in the function (the
	// first instruction is an invisible stack pointer adjustment).
	JMP	start					// JMP	2

// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

// This contains the majority of valid opcode combinations
// available in cmd/internal/obj/ppc64/asm9.go with
// their valid instruction encodings.

#include "../../../../../runtime/textflag.h"

// In case of index mode instructions, usage of
// (Rx)(R0) is equivalent to (Rx+R0)
// In case of base+displacement mode instructions if

	MOVWU	X5, (X6)			// ERROR "unsupported unsigned store"
	MOVF	F0, F1, F2			// ERROR "illegal MOV instruction"
	MOVD	F0, F1, F2			// ERROR "illegal MOV instruction"
	MOV	X10, X11, X12			// ERROR "illegal MOV instruction"
	MOVW	X10, X11, X12			// ERROR "illegal MOV instruction"
	RORI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"
	SLLI	$64, X5, X6			// ERROR "immediate out of range 0 to 63"

   
   
   *TensorFlow release binaries version 1.6 and higher are prebuilt with AVX instruction sets.*
   
   
   Therefore on any CPU that does not have these instruction sets, either CPU or GPU version of TF will fail to load.
   
   Apparently, your CPU model does not support AVX instruction sets. You can still use TensorFlow with the alternatives given below:
   
      * Try Google Colab to use TensorFlow.

// Copyright 2015 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

// This input was created by taking the instruction productions in
// the old assembler's (7a's) grammar and hand-writing complete
// instructions for each rule, to guarantee we cover the same space.

#include "../../../../../runtime/textflag.h"

TEXT	foo(SB), DUPOK|NOSPLIT, $-8

// Copyright 2015 The Go Authors. All rights reserved.
// Use of this source code is governed by a BSD-style
// license that can be found in the LICENSE file.

// This input was created by taking the instruction productions in
// the old assembler's (5a's) grammar and hand-writing complete
// instructions for each rule, to guarantee we cover the same space.

#include "../../../../../runtime/textflag.h"

TEXT	foo(SB), DUPOK|NOSPLIT, $0

// ADD
//

	MOVB	$255, 4096(R4)        // ebff40000152
	MOVB	$-128, -524288(R5)    // eb8050008052
	MOVB	$1, -524289(R6)       // c0a1fff7ffff41aa60009201a000

	// RX (12-bit displacement) and RXY (20-bit displacement) instruction encoding (e.g: ST vs STY)
	MOVW	R1, 4095(R2)(R3)       // 50132fff
	MOVW	R1, 4096(R2)(R3)       // e31320000150
	MOVWZ	R1, 4095(R2)(R3)       // 50132fff
	MOVWZ	R1, 4096(R2)(R3)       // e31320000150

	MOVQ CR8, (AX)                  // ERROR "invalid instruction"
	MOVQ (AX), CR0                  // ERROR "invalid instruction"
	MOVQ (AX), CR2                  // ERROR "invalid instruction"
	MOVQ (AX), CR3                  // ERROR "invalid instruction"
	MOVQ (AX), CR4                  // ERROR "invalid instruction"
	MOVQ (AX), CR8                  // ERROR "invalid instruction"